l99pm62gxp STMicroelectronics, l99pm62gxp Datasheet - Page 76

• Manufacturer Part Number: l99pm62gxp
• Description: Power Management Ic With Lin And High Speed Can
• Manufacturer: STMicroelectronics

ST SPI
6.1.10
76/102
Read and clear status operation
The ‘Read and Clear Status’ operation starts with a command byte followed 2 data bytes.
The number of data bytes is specified in the <SPI-frame-ID>. The content of the data bytes
is ‘don’t care’. The content of the addressed status register is transferred to SDO within the
same frame (‘in-frame response’) and is subsequently cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all status registers (incl. the
<Global Status> register). The configuration register is read by this operation.
Read and clear status command format
Table 61.
Table 62.
Table 63.
OC0, OC1:operating code (10 for ‘read and clear status’ mode)
A0 to A5:address bits
Format of data shifted out at SDO during read and clear status operation
Table 64.
Table 65.
Global error
flag (GEF)
MSB
MSB
MSB
MSB
D15
Bit 7
1
0
0
Op Code
Read and clear status command format: command byte
Read and clear status command format: data byte 1
Read and clear status command format: data byte 2
Format of data shifted out at SDO during read and clear status: global
status register
Format of data shifted out at SDO during read and clear status:
data byte 1
D14
Comm
01
Bit 6
0
0
error
Not (chip reset
or comm error)
Previous content of addressed register
D13
A5
0
0
Bit 5
Doc ID 17639 Rev 3
A4
D12
0
0
TSD2
Bit 4
A3
D11
0
0
Address
TSD1
Bit 3
A2
0
0
D10
V
Bit 2
1
Fail
A1
D9
0
0
(OV/UV)
V
Bit 1
S
L99PM62GXP
Fail
LSB
LSB
LSB
LSB
D8
A0
Bit 0
0
0
safe
Fail