tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 25

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 12 I
Notes
1. Addresses not shown must not be accessed.
2. X = don’t care.
2003 May 21
ADDRESS
(HEX)
30 Mbits/s up to 3.2 Gbits/s
A-rate
BC
BD
CA
CB
CC
BE
BF
C0
C1
C2
C8
C9
A0
A1
A2
A3
A4
A5
A6
A7
A8
B0
B1
B2
B3
B4
B5
B6
00
01
(1)
2
C-bus registers
INTERRUPT
STATUS
HEADER3
HEADER2
HEADER1
HEADER0
HEADERX3
HEADERX2
HEADERX1
HEADERX0
DMXCNF
DIVCNF
MAINDIV1
MAINDIV0
FRACN2
FRACN1
FRACN0
DCRCNF
LIMLOS1TH
LIMLOS1CNF Limiter 1 loss of signal configuration register; see Table 23
LIMLOS2TH
LIMLOS2CNF Limiter 2 loss of signal configuration register; see Table 24
LIMSLICE1
LIMSLICE2
LIMCNF
IOCNF3
IOCNF2
IOCNF1
IOCNF0
INTMASK
fibre optic receiver
NAME
Interrupt register; see Table 13
Status register; see Table 14
Programmable header, most significant byte
1:10 ratio
Programmable header
1:10 ratio
Programmable header
Programmable header, least significant byte
Programmable header, don’t care, most significant byte
1:10 ratio
Programmable header, don’t care
1:10 ratio
Programmable header, don’t care
Programmable header, don’t care, least significant byte
Demultiplexer configuration register; see Table 15
Octave and loop mode configuration register; see Table 16
Main divider division factor N; most significant byte; range
128 to 511; see Table 17
Main divider division factor N; least significant byte; see Table 18 0000 0000
Fractional divider division factor K; see Table 19
Fractional divider division factor K; see Table 20
Fractional divider division factor K; see Table 21
DCR configuration register; see Table 22
Limiter 1 loss of signal threshold register; range 0 to 255
Limiter 2 loss of signal threshold register; range 0 to 255
Limiter 1 slice level register; range 0 to 255
Limiter 2 slice level register; range 0 to 255
Limiter configuration register; see Table 25
Parallel interface output configuration register 3; see Table 26
Parallel interface output configuration register 2; see Table 27
RF serial I/O configuration register 1; see Table 28
RF serial output configuration register 0; see Table 29
Interrupt masking register; see Table 30
FUNCTION
25
TZA3012AHW
1111 0110
0011 1110
1111 0110
10X XXXX
0010 1000
0010 1000
0000 0000
0000 0000
0000 0000
00XX XXXX
0000 0000
0000 0000
0000 1011
0000 0000
0000 0001
1000 0000
0000 0000
0000 0000
0000 1100
0000 0000
0000 1101
0000 0000
0000 1101
0000 0000
0000 0000
0000 1000
0000 1100
1010 1010
0000 0000
0010 0011
0101 0000
DEFAULT
Product specification
VALUE
WRITE
READ/
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R