tza3012ahw NXP Semiconductors, tza3012ahw Datasheet - Page 20

• Manufacturer Part Number: tza3012ahw
• Description: 30 Mbits/s Up To 3.2 Gbits/s A-ratetm Fibre Optic Receiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
CMOS control inputs
CMOS control inputs UI, INSEL, WINSIZE, DMXR0,
DMXR1, ENBA, ENLOUTQ, ENLINQ and CS(DR0) have
an internal pull-up resistor so that these pins go HIGH
when open circuit, and only go LOW when deliberately
forced. This is also true for pins DR1 and DR2 in
pre-programmed mode (pin UI is LOW). In I
mode (pin UI is HIGH), pins SCL and SDA comply with the
I
Power supply connections
Four separate supply domains (V
V
blocks. Each supply domain should be connected to a
common V
including the exposed die pad, must be connected.
The die pad connection to ground must have the lowest
possible inductance. Since the die pad is also used as the
main ground return of the chip, this connection must also
have a low DC impedance. The voltage supply levels
should be in accordance with the values specified in
Chapters “Characteristics” and “Limiting values”.
All external components should be surface mounted, with
a preferable size of 0603 or smaller. The components
must be mounted as close to the IC as possible.
Interrupt register
The following events are recorded by setting the
appropriate bit(s) in I
(address 00 H):
When register INTERRUPT is polled by an I
action, any set bits are reset. If a condition is still active, the
corresponding bit remains set.
2003 May 21
2
CCA
C-bus interface standard.
Loss of signal on channel 1
Loss of signal on channel 2
DCR frequency locked or unlocked
Limiter channel switching enabled or disabled
High junction temperature.
30 Mbits/s up to 3.2 Gbits/s
A-rate
) provide isolation between the various functional
CC
using a separate filter. All supply pins,
fibre optic receiver
2
C-bus register INTERRUPT
DD
, V
CCD
, V
2
C-bus control
2
C-bus read
CCO
and
20
Status register
The current status of the conditions that are recorded by
register INTERRUPT are indicated by setting the
appropriate bit(s) in I
(address 01H). A bit is set only for the period that the
condition is active and resets when the condition clears.
Register STATUS is polled by an I
Interrupt generation
An interrupt is generated if an interrupt condition sets a bit
in I
bit is not masked by I
(address CCH). Only the high junction temperature
interrupt bit is not masked by default. A generated interrupt
is indicated by an active logic level at pin INT. The active
output level used is set by bit INTPOL in I
register INTMASK. The default is an active LOW level.
Bit INTOUT sets the output mode at pin INT to either
open-drain or to standard CMOS. The default is
open-drain. An active LOW output in open-drain mode
allows several receivers to be connected together, and
requires only one 3.3 k pull-up resistor.
2
C-bus register INTERRUPT (address 00H) and if the
2
2
C-bus register STATUS
C-bus register INTMASK
TZA3012AHW
2
C-bus read action.
Product specification
2
C-bus