lm5066pmhx National Semiconductor Corporation, lm5066pmhx Datasheet - Page 24
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lm5066pmhx
Manufacturer Part Number
lm5066pmhx
Description
High Voltage System Power Management And Protection Ic With Pmbus
Manufacturer
National Semiconductor Corporation
Datasheet
1.LM5066PMHX.pdf
(48 pages)
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POWER GOOD PIN
When the voltage at the FB pin increases above its threshold
the internal pulldown acting on the PGD pin is disabled al-
lowing PGD to rise to V
as shown in
high as 80V, and can be higher or lower than the voltages at
VIN and OUT. VDD is a convenient choice for V
lows interface to low voltage logic and avoids glitching on
PGD during power-up. If a delay is required at PGD, suggest-
ed circuits are shown in
C
In
C
R
lows for equal delays at the two edges, or a short delay at the
rising edge and a long delay at the falling edge.
Setting the output threshold for the PGD pin requires two re-
sistors (R4, R5) as shown in
output voltage is shown in
any other voltage which requires monitoring.
The resistor values are calculated as follows:
Choose the upper and lower threshold (V
at V
As an example, assume the application requires the following
thresholds: V
(HYS)
R4 = 100 kΩ, R5 = 6.55 kΩ
When the R4 and R5 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
PG
PG
PG2
Figure
, while the falling edge is delayed a lesser amount by
OUT
adds delay to the rising edge, but not to the falling edge.
= 2V. The resistor values are:
and C
.
15B, the rising edge is delayed by R
PG
Figure
PGDH
. Adding a diode across R
= 40V, and V
14. The pull-up voltage (V
PGD
Figure
Figure
through the pull-up resistor, R
Figure
15. In
PGDL
13, R4 can be connected to
FIGURE 15. Adding Delay to the Power Good Output Pin
13. While monitoring the
= 38V. Therefore V
Figure
PG2
PGDH
(Figure
PG1
PGD
15A, capacitor
) and (V
PGD
) can be as
+ R
15C) al-
PG2
as it al-
PGDL
and
PGD
PG
)
,
24
FIGURE 13. Programming the PGD Threshold
FIGURE 14. Power Good Output
30115951
301159a5
30115952