m58wr032et STMicroelectronics, m58wr032et Datasheet - Page 11

• Manufacturer Part Number: m58wr032et
• Description: 32 Mbit 2mb X 16, Multiple Bank, Burst 1.8v Supply Flash Memory
• Manufacturer: STMicroelectronics

SIGNAL DESCRIPTIONS
See
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at V
mode. When Chip Enable is at V
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at V
and the Locked-Down blocks can be locked or un-
locked. (refer to
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current I
Table 18., DC Characteristics - Currents
value of I
Locked state and the Configuration Register is re-
set. When Reset is at V
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to
IL
Figure 2., Logic Diagram
and Reset is at V
Table 19., DC Characteristics -
DD2.
After Reset all blocks are in the
Table 13., Lock
IH
, the Lock-Down is disabled
IH
IH
, the device is in normal
the device is in active
and
Status).
IH
Table 1., Signal
the memory is
DD2
IL
, the Lock-
Voltages).
. Refer to
for the
RPH
IL
,
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
V
V
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at V
don't care during asynchronous read and in write
operations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at V
It can be configured to be active during the wait cy-
cle or one clock cycle in advance. The WAIT signal
is not gated by Output Enable.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
supply to the I/O pins and enables all Outputs to
be powered independently from V
tied to V
V
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If V
V
age lower than V
against program or erase, while V
ables these functions (see Tables
Characteristics for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase op-
erations continue.
If V
supply pin. In this condition V
til the Program/Erase algorithm is completed.
V
core supply. It must be connected to the system
ground.
V
the input/output circuitry driven by V
must be connected to V
Note: Each device in a system should have
V
DD
DDQ
PP
PP
SS
SSQ
DD
IL
IH
PP
. Latch Enable can be kept Low (also at
PP
and it is inhibited when Latch Enable is at
, V
Program Supply Voltage. V
Ground. V
Supply Voltage . V
is seen as a control input. In this case a volt-
Ground. V
Supply Voltage. V
is kept in a low voltage range (0V to V
DDQ
is in the range of V
DD
or can use a separate supply.
and V
M58WR032ET, M58WR032EB
SS
PPLK
SSQ
PP
ground is the reference for the
decoupled with a 0.1µF ce-
gives an absolute protection
ground is the reference for
SS
DD
DDQ
PPH
PP
provides the power
IH
provides the power
it acts as a power
must be stable un-
or Reset is at V
DD
PP
18
PP
. V
and 19, DC
is both a
> V
DDQ
DDQ
IL
PP
. Clock is
PP1
. V
can be
is only
11/81
DDQ
SSQ
en-
IL
)
.