s-24c02ci-t8t1u Seiko Instruments Inc., s-24c02ci-t8t1u Datasheet - Page 19

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s-24c02ci-t8t1u

Manufacturer Part Number
s-24c02ci-t8t1u
Description
2-wire Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet

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LINE
SDA
Rev.2.0
ADDRESS
DEVICE
7. 3 Sequential Read
When the E
start condition both in current address read and random read, it responds with an acknowledge.
An 8-bit data is then sent from the E
automatically incremented at the falling edge of the SCL clock for the 8th bit data.
When the master device responds with an acknowledge, the data at the next memory address is transmitted.
Response with an acknowledge by the master device has the memory address counter in the E
incremented and makes it possible to read data in succession. This is called “Sequential Read”.
The master device outputs stop condition not an acknowledge, the reading of E
Data can be read in succession in the sequential read mode. When the memory address counter reaches the last
word address, it rolls over to the first word address.
_00_C
W
R
E
A
D
1
R
/
C
A
K
D7
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a
DATA (n)
ADR INC
D0
A
C
K
D7
Figure 20 Sequential Read
DATA (n + 1)
Seiko Instruments Inc.
2
PROM synchronous to the SCL clock and the address counter is
ADR INC
D0
C
A
K
D7
DATA (n + 2)
2-WIRE CMOS SERIAL E
ADR INC
2
PROM is ended.
D0
A
C
K
D7
Master Device
NO ACK from
DATA (n + x)
S-24C01C/02C
ADR INC
2
PROM
D0
2
PROM
19
O
S
T
P

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