lh28f640 Sharp Microelectronics of the Americas, lh28f640 Datasheet - Page 6

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lh28f640

Manufacturer Part Number
lh28f640
Description
64m X16 Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet

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DQ
Symbol
A
RST#
GND
WE#
CE#
OE#
V
0
0
-A
-DQ
CC
21
15
OUTPUT
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses. 64M: A
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code and
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (V
standby levels.
RESET: When low (V
which provides data protection. RST#-high (V
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
DEVICE POWER SUPPLY (2.7V-3.6V): With V
flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
GROUND: Do not float any ground pins.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
Table 1. Pin Descriptions
LHF64FZ2
IL
), RST# resets internal automation and inhibits write operations
IH
) deselects the device and reduces power consumption to
Name and Function
IH
0
CC
-A
) enables normal operation. After
21
V
LKO
, all write attempts to the
CC
voltage (see DC
Rev. 2.41
4

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