lh28f128bfht-pbtl75a Sharp Microelectronics of the Americas, lh28f128bfht-pbtl75a Datasheet
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... RELIMINARY RODUCT PECIFICATION LH28F128BFHT- PBTL75A Flash Memory 16Mbit (8Mbitx16) (Model Number: LHF12F17) Spec. Issue Date: June 7, 2004 Integrated Circuits Group ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, ...
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... TSOP (Normal Bend) Pinout ....................... 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with 6 Planes........................................ 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 9 OTP Block Address Map for OTP Program............. 10 Bus Operation............................................................ 11 Command Definitions .............................................. 12 Functions of Block Lock and Block Lock-Down..... 14 Block Locking State Transitions upon Command Write ...
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... LH28F128BFHT-PBTL75A Page Mode Dual Work Flash MEMORY 128-M density with 16-bit I/O Interface High Performance Reads • 75/25ns 8-Word Page Mode 6-Plane Dual Work Operation • Read operations are available during Block Erase or (Page Buffer) Program between two different Planes • Plane Architecture: ...
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WE# 13 RST ...
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... ADDRESS INPUTS: Inputs for addresses. INPUT 22 0 DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User INPUT/ Interface) write cycles, outputs data during memory array, status register, query code and DQ - OUTPUT identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. CHIP ENABLE: Activates the device’ ...
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Table 2. Simultaneous Operation Modes Allowed with 6 Planes THEN THE MODES ALLOWED IN THE OTHER PLANE IS: IF ONE Read Read Read PLANE IS: Array ID/OTP Status Read Array Read ID/OTP Read Status ...
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... Block 43 120000H - 127FFFH 32-Kword Block 42 118000H - 11FFFFH 32-Kword Block 41 110000H - 117FFFH 32-Kword Block 40 108000H - 10FFFFH 32-Kword Block 39 100000H - 107FFFH PLANE1 : 24 Mbit Figure 2.1. Memory Map (Bottom Parameter, Plane 0 and Plane 0F8000H - 0FFFFFH 32-Kword Block 38 0F0000H - 0F7FFFH 32-Kword Block 37 0E8000H - 0EFFFFH ...
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... Block 138 418000H - 41FFFFH 32-Kword Block 137 410000H - 417FFFH 32-Kword Block 136 408000H - 40FFFFH 32-Kword Block 135 400000H - 407FFFH PLANE3 : 24 Mbit Figure 2.2. Memory Map (Bottom Parameter, Plane 2 and Plane 32-Kword Block 134 3F8000H - 3FFFFFH 32-Kword Block 133 3F0000H - 3F7FFFH ...
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... Block 2 4 710000H - 717FFFH 2-Kword Block 2 708000H - 70FFFFH 2-Kword Block 2 2 700000H - 707FFFH 2-Kword Block 2 1 PLANE5 : 16 Mbit Figure 2.3. Memory Map (Bottom Parameter, Plane 4 and Plane 6F8000H - 6FFFFFH 2-Kword Block 2 0 6F0000H - 6F7FFFH 2-Kword Block 229 ...
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Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down OTP OTP Lock OTP NOTES: ...
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LHF12F17 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ - Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP ...
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Table 4. Bus Operation Mode Notes RST# CE# Read Array Output Disable Standby Reset Read Identifier Codes/OTP V V Read Query 6,7 ...
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... Refer to Appendix of LH28F128BF series for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See Figure 3). ...
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Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H the program operation ...
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Table 6. Functions of Block Lock Current State (1) State WP#/ACC DQ 1 [000 ( [001] [011 [100 ( [101] ( [110] [111 NOTES ...
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Table 8. Block Locking State Transitions upon WP#/ACC Transition Current State Previous State State WP#/ACC - [000 [001] 0 (2) [110] [011] 0 Other than (2) [110] - [100 [101 [110 [111] ...
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GWSMS GBESS GBEFCES PWSMS GBESS GBEFCES SR.7 = PLANE WRITE STATE MACHINE STATUS (PWSMS Ready 0 = Busy SR.6 = GLOBAL BLOCK ERASE SUSPEND STATUS (GBESS Block Erase Suspended 0 ...
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Table 9.2. Status Register Definition (Continued) SR.15 = GLOBAL WRITE STATE MACHINE STATUS (GWSMS Ready 0 = Busy SR.14 = GLOBAL BLOCK ERASE SUSPEND STATUS (GBESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.13 ...
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Table 10. Extended Status Register Definition SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page ...
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Electrical Specifications 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except ...
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Capacitance (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance C IN WP#/ACC Input Capacitance C IN Output Capacitance C OUT NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT 0.0 AC test inputs ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Automatic Power CC I CCAS Current I V Reset Current CCD CC Average V Read CC Current Normal ...
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... Sampled, not 100% tested. 5. Applying 9.5V±0.5V to WP#/ACC provides fast erasing or fast programming mode. In this mode, WP#/ACC is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the V Applying 9.5V± ...
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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...
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(A) 22 EHEL V IH (E) CE AVEL t AVGL t GHGL V IH OE# ( (W) WE High (D/Q) 15-0 ...
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(A) 22 (A) 2 CE# ( OE# ( WE# ( High (D/Q) 15-0 V ...
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(A) 22 AVQV V IH VALID A (A) 2-0 ADDRESS CE# ( ELQV V IH OE# ( WE# ( GLQX ...
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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...
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NOTE 1 NOTE VALID A (A) 22-0 ADDRESS CE# ( ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# (W) ...
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Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...
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Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4-Kword Parameter Block t WPB Program Time 32-Kword Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...