m45pe10 STMicroelectronics, m45pe10 Datasheet - Page 21

• Manufacturer Part Number: m45pe10
• Description: 1 Mbit, Page-erasable Serial Flash Memory With Byte-alterability And 75 Mhz Spi Bus Interface
• Manufacturer: STMicroelectronics

M45PE10
6.5
Figure 9.
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on serial data output (Q), each bit being shifted out, at a maximum
frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an erase, program or write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
S
C
D
Q
R
, during the falling edge of Serial Clock (C).
Read status register (RDSR) instruction sequence and data-out sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
Figure
6
Status Register Out
9 10 11 12 13 14 15
5
4
10.
3
2
1
0
MSB
7
6
Status Register Out
5
4
3
2
1
Instructions
0
7
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