m34e02 STMicroelectronics, m34e02 Datasheet - Page 17

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m34e02

Manufacturer Part Number
m34e02
Description
2 Kbit Serial I?c Bus Eeprom With Permanent And Reversible, Software Write Protection
Manufacturer
STMicroelectronics
Datasheet

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M34E02
3.7.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
can be used by the bus master.
The sequence, as shown in
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table
12, but the typical time is shorter. To make use of this, a polling sequence
Figure
9, is:
Device operation
w
) is
17/33

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