is42s16100c1 Integrated Silicon Solution, Inc., is42s16100c1 Datasheet - Page 33

• Manufacturer Part Number: is42s16100c1
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S16100C1
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100C1 can output data continuously from the
burst start address (a) to location a+255 during a read cycle
in which the burst length is set to full page. The
IS42S16100C1 repeats the operation starting at the 256th
cycle with the data output returning to location (a) and
continuing with a+1, a+2, a+3, etc. A burst stop command
must be executed to terminate this cycle. A precharge
command must be executed within the ACT to PRE
command period (t
command.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. D
11/03/06
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
RAS
READ A0
READ A0
max.) following the burst stop
D
OUT
A0 D
D
OUT
OUT
1-800-379-4774
A0
A0 D
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
CAS latency is two and three clock cycle when the CAS
latency is three.
D
OUT
OUT
CAS
CAS
CAS
CAS
CAS Latency
A1
A0
BURST STOP
BURST STOP
t
RBD
D
D
OUT
OUT
BST
BST
A2
RBD
A1
RBD
) required for burst data output to
t
RBD
D
D
) is two clock cycle when the
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
A3
ISSI
HI-Z
2
2
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