is42s16100c1 Integrated Silicon Solution, Inc., is42s16100c1 Datasheet - Page 30

• Manufacturer Part Number: is42s16100c1
• Description: 512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
• Manufacturer: Integrated Silicon Solution, Inc.

30
IS42S16100C1
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding to
the new write command can be input at the point new
write command is executed. To prevent collision
between input and output data at the DQn pins during
this operation, the
CAS latency = 2, 3, burstlength = 4
COMMAND
U/LDQM
CLK
DQ
READ (CA=A, BANK 0)
READ A0
HI-Z
D
WRITE B0
IN
t
CCD
B0
Integrated Silicon Solution, Inc. — www.issi.com —
WRITE (CA=B, BANK 0)
D
IN
B1
D
output data must be masked using the U/LDQM pins. The
interval (t
one clock cycle.
The selected bank must be set to the active state before
executing this command.
IN
B2
CCD
D
IN
) between these commands must be at least
B3
ISSI
1-800-379-4774
11/03/06
Rev. D
®