at49ll040 ATMEL Corporation, at49ll040 Datasheet - Page 7

• Manufacturer Part Number: at49ll040
• Description: 4-megabit Low-pin Count Flash Memory
• Manufacturer: ATMEL Corporation

3343A–FLASH–6/03
START: This one-clock field indicates the start of a cycle. It is valid on the last clock that
LFRAME is sampled low. On the rising edge of CLK with LFRAME low, the contents of
LAD3 - LAD0 must be 0000b to indicate the start of a LPC cycle.
Table 3. CYCTYPE + DIR Fields
CYCTYPES + DIR: This one-clock field is used to indicate the type of cycle and direc-
tion of transfer. Bits 3 - 2 must be “01b” for a memory cycle. Bit 1 indicates the type of
transfer: “0” for read operation, “1” for write operation. DIR field indication of transfer: “0”
for read, “1” for write. Bit 0 is reserved. “010xb” indicates a memory read cycle; while
“011xb” indicates a memory write cycle.
MADDR (MEMORY ADDRESS): This is an eight-clock field, which gives a 32-bit mem-
ory address. LPC supports the 32-bit address protocol. The address is transferred with
the most significant nibble first. Address bit 23 directs Reads and Writes to memory
locations (A
device ID strapping bits, and A
TURN-AROUND (TAR): This field is two clocks wide, and is driven by the master when
it is turning control over to the LPC, (for example, to read data), and is driven by the LPC
when it is turning control back over to the master. On the first clock of this two-clock-
wide field, the master or LPC drives the LAD[3:0] lines to “1111b”. On the second clock
of this field, the master or peripheral tri-states the LAD[3:0] lines.
SYNC: This field is used to add wait states. It can be several clocks in length. On target
or DMA cycles, this field is driven by the LPC. If the LPC needs to assert wait states, it
does so by driving “0101b” (short SYNC) on LAD[3:0] until it is ready. When ready, it will
drive “0000b”. Valid values for this field are shown in Table 4.
Table 4. Valid SYNC Values
LAD[3:0]
010xb
011xb
Bits[3:0]
0000
0101
23
= 1) or to register access locations (A
Indication
Ready: SYNC achieved with no error.
Short Wait: Part indicating wait states.
Indication
LPC Memory Read
LPC Memory Write
18
- A
0
are decoded as memory addresses.
23
= 0), address bits A
AT49LL040
22
- A
19
are
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