at49ll040 ATMEL Corporation, at49ll040 Datasheet

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... Industry-standard Package – 40-lead TSOP or 32-lead PLCC Description The AT49LL040 is a Flash memory device designed to interface with the LPC bus for PC Applications. A feature of the AT49LL040 is the nonvolatile memory core. The high-performance memory is arranged in eleven sectors (see page 10). The AT49LL040 supports two hardware interfaces: Low Pin Count (LPC) for in-system operation and Address/Address Multiplexed (A/A Mux) for programming during manu- facturing ...

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... Low Pin Count Interface Address/Address Multiplexed Interface Block Diagram AT49LL040 2 The VPP pin gives complete data protection when V together for a simple, low-power 3V design. Programming board solutions should design such that V draws from the same supply ming current may be drawn from either pin. ...

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... LPC mode. Any ID pins that are pulled high will exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be left to float single LPC system, all may be left floating. A/A Mux = A[3:0] AT49LL040 + 0.3V max, unless otherwise noted ...

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... Since this pin is internally pulled down and thus can be left unconnected, the AT49LL040 is compatible with systems that do not use a CE signal. To reduce power, the device is placed in a low-power standby mode when CE is high. ...

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... DMA channel, and bus master grant. LFRAME: LFRAME is used by the master to indicate the start of cycles and the termina- tion of cycles due to an abort or time-out condition. This signal used be by peripherals to know when to monitor the bus for a cycle. AT49LL040 . IL Description Multiplexed command, address and data Indicates start of a new cycle, termination of broken cycle ...

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... LPC memory may be providing status information instead of memory array data). CYCLE TYPES: There are two types of cycles that are supported by the AT49LL040: LPC Memory Read and LPC Memory Write. READ: Read operations consist of START, CYCTYPE + DIR, ADDRESS, TAR, SYNC and data fields as shown in Figure 1 and described in Table 5 ...

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... Valid values for this field are shown in Table 4. Table 4. Valid SYNC Values Bits[3:0] Indication 0000 Ready: SYNC achieved with no error. 0101 Short Wait: Part indicating wait states. AT49LL040 = 0), address bits A 23 are decoded as memory addresses are 22 19 ...

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... CYCTYPE + DIR ADDR 11 TAR0 12 TAR1 WSYNC 15 RSYNC 16 DATA 17 DATA 18 TAR0 19 TAR1 Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LL040 ADDR TAR SYNC(3) (1) Field Contents LAD[3:0] LAD[3:0] Direction 0000b IN 010xb IN YYYY IN ...

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... Flash command. 1111b OUT The LPC Flash memory drives LAD0 - LAD3 to 1111b to indicate then Float a turnaround cycle. Float then The LPC Flash memory floats its outputs, the master (ICH) takes IN control of LAD3 - LAD0. AT49LL040 TAR SYNC TAR 9 ...

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... Bus Abort AT49LL040 10 OUTPUT DISABLE: When the LPC is not selected through a LPC read or write cycle, the LPC interface outputs (LAD[3:0]) are disabled and will be placed in a high-imped- ance state. The Bus Abort operation can be used to immediately abort the current bus operation. A ...

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... A series of registers are available in the LPC to provide software read and write locking and GPI feedback. These registers are accessible through standard addressable mem- ory space. REGISTERS: The AT49LL040 has two types of registers: sector-locking registers and general-purpose input registers. The two types of registers appear at their respective address locations in the 4 GB system memory map. ...

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... Changing the state of the Write Lock bit during a program or erase operation may cause unpredictable results. The new lock status will take place after the program or erase operation completes. The individ- ual bit functions are described in the following sections. AT49LL040 12 Lock-down, ...

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... Bus Cycle Operation Addr 1 Write XXXX 2 Write SA 2 Write SA 2 Write Addr 2 Write XXXX 2 Write XXXX 1 Write XXXX AT49LL040 2nd Bus Cycle Data Operation Addr FF 20 Write SA 21 Write Write Addr (7) 90 Read AID 70 Read XXXX 50 Data D0 ...

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... SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased state of the memory bits is a logical “1”. Since the AT49LL040 does not offer a complete chip erase, the device is organized into multiple sectors that can be individually erased. The device incorporates two erase commands that allow either a Main Sector (64K bytes erased or allow a Parametric/Boot Sector (32K/16K/8K bytes erased ...

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... The AT49LL040 is designed to offer a parallel programming mode for faster factory pro- gramming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is pulled down internally in the AT49LL040 modest current should be expected to be drawn (see Table 1 on page 3 for further information). Four control pins dictate data flow in and out of the component: R/C, OE, WE, and RST ...

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... AT49LL040 16 Bus Operations Mode RST OE (1)(5) Read (5) Output Disable (5) Product ID Entry (3)(4)(5) Write Notes can for control and address input pins and pin. See the “DC Characteristics” for V 2. See Table 11 on page 14 for Product ID Entry data and addresses. ...

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... OUT I = 1500 µA OUT AT49LL040 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...

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... All currents are in RMS unless otherwise noted. These currents are valid for all packages 0 0 This number is the worst case of I AT49LL040 18 Conditions (2) Voltage range of all inputs LFRAME = 3.6V, CC CLK MHz No internal operations in ...

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... IN CC (1) 0 0.6 V load CC CC (1) 0 0.2 V load *( OUT OUT Condition peak-to-peak t CYC t HIGH 0 0.2 V AT49LL040 Min Max - -17 OUT Note 2 - -17 OUT Note - 1)/0.015 1)/0.015 Min ...

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... For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK). Output Timing Parameters (Valid Output Data) (Float Output Data) Input Timing Parameters LAD[3:0] (Valid Input Data) AT49LL040 20 (1) (2) (2) (3) (3) (2) CLK ...

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... Excludes system-level overhead. 3343A–FLASH–6/03 of overdrive over V CC specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production t PLPH (1) Typ 30.0 2.0 0.8 = +25 C and nominal voltages. A AT49LL040 Value V/ns and V . Timing parameters must be met with no more IH ...

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... V IH RST V IL AT49LL040 22 ELECTRICAL CHARACTERISTICS IN A/A MUX MODE: Certain specifications differ from the previous sections, when programming in A/A Mux Mode. The following subsec- tions provide this data. Any information that is not shown here is not specific to A/A Mux Mode and uses the LPC Mode specifications. ...

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... R/C without impact on t GLQV . CC t AVAV Row Address Column Address Stable Stable t AVCL t t CLAX AVCH t CHAX t CHQV PHAV High-Z t GLQX AT49LL040 Min Max 250 150 CHQV Next Address Stable t GLQV t GHQZ t QXGH ...

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... NOTES power-up and standby Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command AT49LL040 24 (1) (1) (1) (1) and D for sector erase or program, or other commands ...

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... AT49LL040 Ordering Information I (mA) CC Active Standby 67 0.10 32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Plastic Thin Small Outline Package, Type I (TSOP) 3343A–FLASH–6/03 Ordering Code AT49LL040-33JC AT49LL040-33TC Package Type AT49LL040 Package Operation Range 32J Extended Commercial 40T ( ...

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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LL040 26 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

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... Orchard Parkway San Jose, CA 95131 R 3343A–FLASH–6/03 PIN SEATING PLANE A1 TITLE 40T, 40-lead ( Package) Plastic Thin Small Outline Package, Type I (TSOP) AT49LL040 0º ~ 8º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – ...

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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...