at49ll040 ATMEL Corporation, at49ll040 Datasheet - Page 4

• Manufacturer Part Number: at49ll040
• Description: 4-megabit Low-pin Count Flash Memory
• Manufacturer: ATMEL Corporation

Table 1. Pin Description (Continued)
4
Symbol
CE
GPI[4:0]
TBL
WP
A0 - A10
I/O0 - I/O7
OE
R/C
WE
V
PP
AT49LL040
SUPPLY
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
I/O
LPC
X
X
X
X
X
Interface
A/A Mux
X
X
X
X
X
X
Name and Function
When CE is low, the device is enabled. This pin is pulled down with an
internal resistor and can exhibit a leakage current of approximately 10 µA.
Since this pin is internally pulled down and thus can be left unconnected, the
AT49LL040 is compatible with systems that do not use a CE signal. To reduce
power, the device is placed in a low-power standby mode when CE is high.
GENERAL PURPOSE INPUTS: These individual inputs can be used for
additional board flexibility. The state of these pins can be read through LPC
registers. These inputs should be at their desired state before the start of the
PCI clock cycle during which the read is attempted, and should remain at the
same level until the end of the read cycle. They may only be used for 3.3V
signals. Unused GPI pins must not be floated.
A/A Mux = A[10:6]
TOP SECTOR LOCK: When low, prevents programming or sector erase to the
highest addressable sector (10) regardless of the state of the lock registers TBL
high disables hardware write protection for the top sector, though register-
based protection still applies. The status of TBL does not affect the status of
sector-locking registers.
A/A Mux = A4
WRITE-PROTECT: When low, prevents programming or sector erase to all but
the highest addressable sectors (0 - 9), regardless of the state of the
corresponding lock registers. WP-high disables hardware write protection for
these sectors, though register-based protection still applies. The status of TBL
does not affect the status of sector-locking registers.
A/A Mux = A5
LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during read
and write operations. Addresses are internally latched during a write cycle. For
the A/A Mux interface these addresses are latched by R/C and share the same
pins as the high-order address inputs.
DATA INPUT/OUTPUTS: These pins receive data and commands during write
cycles and transmit data during memory array and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
ROW-COLUMN ADDRESS SELECT: For the A/A Mux interface, this pin
determines whether the address pins are pointing to the row addresses,
A0 - A10, or to the column addresses A11 - A18.
WRITE ENABLE: Controls writes to the array sectors. Addresses and data are
latched on the rising edge of the WE pulse.
SECTOR ERASE/PROGRAM POWER SUPPLY: The VPP pin can be left
unconnected. Sector erase or program with an invalid V
Characteristics) produces spurious results and should not be attempted.
PP
(see DC
3343A–FLASH–6/03