at49ll040 ATMEL Corporation, at49ll040 Datasheet - Page 15

• Manufacturer Part Number: at49ll040
• Description: 4-megabit Low-pin Count Flash Memory
• Manufacturer: ATMEL Corporation

A/A Mux Interface
3343A–FLASH–6/03
READ STATUS REGISTER: The status register may be read to determine when a sec-
tor erase or program completes and whether the operation completed successfully. The
status register may be read at any time by writing the Read Status Register command.
After writing this command, all subsequent read operations will return data from the sta-
tus register until another valid command is written. The Read Status Register command
functions independently of the V
CLEAR STATUS REGISTER: Error flags in the status register can only be set to “1”s by
the WSM and can only be reset by the Clear Status Register command. These bits indi-
cate various failure conditions. The Clear Status Register command functions
independently of the applied V
Status Register Definition
Notes:
The following information applies only to the AT49LL040 when in A/A Mux Mode. Infor-
mation on LPC Mode (the standard operating mode) is detailed earlier in this document.
Electrical characteristics in A/A Mux Mode are provided on pages starting from page 22.
The AT49LL040 is designed to offer a parallel programming mode for faster factory pro-
gramming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The
IC pin is pulled down internally in the AT49LL040, so a modest current should be
expected to be drawn (see Table 1 on page 3 for further information). Four control pins
dictate data flow in and out of the component: R/C, OE, WE, and RST. R/C is the A/A
Mux control pin used to latch row and column addresses. OE is the data output control
pin (I/O0 - I/O7), drives the selected memory data onto the I/O bus, when active WE and
RST must be at V
BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most auto-
mated test equipment and PROM programmers.
B7
B5
B4
B1
B0
1. Check B7 to determine sector erase or program completion. B6 - B0 are invalid while
2. If both B5 and B4 are “1”s after a sector erase attempt, an improper command
3. B1 does not provide a continuous indication of Write Lock bit, TBL pin or WP pin val-
4. B0 is reserved for future use and should be masked out when polling the status
5. B2 = B6 = 0.
Write State Machine Status
Erase Status
Program Status
Device Protect Status
Reserved for Future Enhancements
B7 = “0”.
sequence was entered.
ues. The WSM interrogates the Write Lock bit, TBL pin or WP pin only after a sector
erase or program operation. Depending on the attempted operation, it informs the
system whether or not the selected sector is locked.
register.
IH
.
(2)
(3)
PP
PP
voltage.
voltage.
(1)
(4)
1
0
1
0
1
0
1
0
Ready
Busy
Error in Sector Erasure
Successful Sector Erase
Error in Program
Successful Program
Write Lock Bit, TBL Pin or WP Pin
Detected, Operation Abort
Unlock
AT49LL040
15