at49ld3200 ATMEL Corporation, at49ld3200 Datasheet - Page 26

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at49ld3200

Manufacturer Part Number
at49ld3200
Description
At49ld3200 32-megabit 1m X 32 Or 2m X 16 High-speed Synchronous Flash Memory
Manufacturer
ATMEL Corporation
Datasheet

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Detailed Functional Truth Table
Note:
26
Current
State
After
Power-up
Row Active
READ
Any State
Any State
Any State
1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip
(1)
AT49LD3200(B)
enters normal operation mode.
CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
CS
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
Input Signal
H
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
CAS
X
H
H
X
H
H
H
X
H
L
L
L
L
L
L
L
L
MR
H
H
H
H
H
H
H
H
X
L
L
X
L
L
L
X
L
Code
Code
Code
Add.
RA
RA
CA
RA
CA
CA
X
X
X
X
X
X
X
X
Next State Operation
Power-down
Row Active; latch RA
Mode Register Set
If consecutive row access is issued within t
without CAS enabling, only the final RA is valid.
Begin READ; latch CA
Illegal
Clock Suspend
Row Access in Read State, within the t
read is ignored and new row is activated. Beyond the
t
begins.
Consecutive Column Access, within the t
the final CA is valid and the previous burst read is
ignored. Beyond the t
completed and new read begins.
NOP (after Burst Read)/Read Interrupt
NOP (after Burst Read)/Read Interrupt
Illegal
Clock Suspend/Power-down
Low Power Consumption Mode
NOP
Illegal
Illegal
RC
, previous read is completed and new read
(1)
(1)
VCVC
, the previous read is
1940B–FLASH–11/01
RC
VCVC
, previous
RC
, only
(min.)

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