at49ld3200 ATMEL Corporation, at49ld3200 Datasheet
at49ld3200
Available stocks
Related parts for at49ld3200
at49ld3200 Summary of contents
Page 1
... The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up, whereas with the AT49LD3200, the Asynchronous Boot Block can be acti- vated through Mode Register Set. The synchronous DRAM interface allows designers to maximize system performance while eliminating the need to shadow slow asynchronous Flash memory into high- speed RAM ...
Page 2
... Pin Configuration AT49LD3200( maximize system manufacturing throughput the AT49LD3200(B) features high- speed 12-volt program and erase options. Additionally, stand-alone programming cycle time of individual devices or modules is optimized with Atmel’s unique input and output pin continuity test mode. VCC 1 DQ0 2 VCCQ ...
Page 3
... WORD = low, word mode). Should be set to the desired state during power-up and prior to any device operation. Masks output operation when a complete burst is not required. Not connected Enables the chip to be written. Program/Erase power supply. AT49LD3200( (x32 (x16) 0 ...
Page 4
... Respect to Ground .....................................-0.6V to +4.6V All Output Voltages with Respect to Ground .............................-0. Voltage with Respect to Ground ...................................-0.6V to +13.5V Power Dissipation .............................................................. 1 W Functional Block Diagram Program/ WE Erase VPP Logic CLK ADD LCKE AT49LD3200(B) 4 *NOTICE: + 0.6V CC DQ0 DQ16 IO Buffer ADD LRAS LRAS LMR LCAS Timing Register CLK CKE ...
Page 5
... Pins not under test = 0V (0V £ V £ V Max) OUT OUT DD All Outputs in High-Z (1) Note (2) Note (max) and V IL AT49LD3200(B) AT49LD3200(B)-13 AT49LD3200(B)-20 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C 3.0V to 3.6V 3.0V to 3.6V Min Max 150 -10 10 - 0.3 DD -0.3 ...
Page 6
... AT49LD3200(B) 6 Figure 1. DC Output Load Circuit Output 870Ω Figure 2. AC Output Load Circuit Output (1) Pin Capacitance MHz 25°C Symbol Typ ( OUT Notes: 1. This parameter is characterized and is not 100% tested behaves as an output pin. PP 3.3V 1200Ω ...
Page 7
... CLKs for MHz. Refer to page 27 for gapless operation. VCVC 1940B–FLASH–11/01 <100 MHz Min Max ( 0 CLKs for up to 100 MHz CLKs for up to 100 MHz, t VCVC AT49LD3200(B) <75 MHz <50 MHz Min Max Min 6 ...
Page 8
... Data is provided through will output Manufacturer Code/Device Code “H” The user can tie MR and WE together to simplify the interface of the AT49LD3200(B) onto the standard SDRAM bus. AT49LD3200(B) 8 CKEn-1 CKEn CS RAS CAS ...
Page 9
... Reserved AT49LD3200(B) MR DQM Add. WORD X L Add Add Add Burst Type Burst Length Burst Type Burst Length A2 Type ...
Page 10
... MSB Address Register Address Notes: 1. For X16 operation, when set to High, data belonging 31th registers are output Asynchronous Boot Block uses x16 operation and A AT49LD3200( ...
Page 11
... I The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high during all cycles, except for power-down, standby and clock suspend mode. If CKE goes ...
Page 12
... Mode Register Set before entering normal operation mode. The mode register is repro- grammed by asserting low on CS, RAS, CAS and MR (the AT49LD3200(B) should be in active mode with CKE already high prior to writing the mode register). The state of ...
Page 13
... Before a word/double word can be reprogrammed, it must be erased. The erased state of the memory bits is a logical “1”. The AT49LD3200(B) is organized into eight uniform four megabit sectors (SA0 - SA7) that can be individually erased. The Sector Erase command is a synchronous six-bus cycle operation (refer to the Command Definition table and Program Cycle and Erase Cycle waveforms) ...
Page 14
... Atmel product. The AT49LD3200(B) features DATA polling to indicate the end of a program or sector erase cycle. DATA polling may begin at any time during the program or sector erase cycle ...
Page 15
... CLK WE VPP The AT49LD3200B will automatically activate the Asynchronous Boot Block after power-up and the AT49LD3200 can activate the Asynchronous Boot Block through the Mode Register Set. The size of the boot block bits with addresses A and outputs The contents of the boot block are accessed asynchronously, ...
Page 16
... AT49LD3200(B) 16 Boot Block Lockout command, which is a synchronous five-bus cycle operation, must be performed (refer to Command Definitions table and Program Cycle Waveforms). A software method is available to determine if programming or erasing of the boot block is locked out. Issue Boot Block Lockout Verify command and observe DQ data show 00H/02H, the boot block can be programmed or erased; if the data show 01H/03H, the lockout feature has been enabled and the boot block cannot be pro- grammed or erased ...
Page 17
... 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K 256K/128K AT49LD3200(B) 4th Bus Cycle 5th Bus Cycle RA CA Data RA CA Data ...
Page 18
... Clock Suspend Exit and Power-down Exit 1) Clock Suspend Exit CLK CKE Internal CLK CMD Note: After Mode Register Set command is completed, no new commands can be issued for 3 clock cycles, and should be fixed “H” within a minimum of 3 clock cycles. AT49LD3200(B) 18 ACT (1) 3CLK Masked by CKE ...
Page 19
... Masked by DQM High High High DQM to Data-out Mask = 2CLKs (1) High-Z High High-Z High High-Z High AT49LD3200(B) High High High ...
Page 20
... RAS Latency tSH RAS t SS CAS t SH ADDR RAa CAa clocks at BL=4 RC Data MR Row Active Read Note: When the burst length MHz, t AT49LD3200( HIGH RAb CAb ( DQa0 DQa1 DQa2 DQa3 t t ...
Page 21
... When column access is initiated beyond t 1940B–FLASH–11/ HIGH CAb DQa0 DQa1 DQa2 DQa3 t SAC Read , access read is completed, CA VCVC a AT49LD3200( DQb0 DQb1 DQb2 DQb3 t SHZ : Don't Care access read begins ...
Page 22
... CAa clocks at BL=4 VCVC Burst Length=4 Data MR Row Active Read Notes: 1. From next clock after CKE goes low, clock suspension begins. 2. For clock suspension, data output state is held and maintained. AT49LD3200( (1) (2) DQa2 DQa3 DQa0 DQa1 ...
Page 23
... HIGH CAb (1) DQa0 DQa1 DQa2 DQa3 DQa4 (2) DQa0 DQa1 DQa2 DQa3 DQa4 (1)(2) Burst Stop Read AT49LD3200( (1) DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 Precharge : Don't Care 19 (2) 23 ...
Page 24
... MR Power-down Power-down Entry Notes: 1. From next clock after CKE goes low, clock suspend and power-down begins. 2. After power-down exit, NOP should be issued and new command can be issued after 1 clock. 3. Clock suspend is in active standby mode. AT49LD3200( ...
Page 25
... Mode Register Set, user must exit from power-down mode and start Mode Register Set before chip enters normal operation mode. 1940B–FLASH–11/ HIGH RAa CAa Data High-Z State Row Active AT49LD3200( DQa0 DQa1 DQa2 DQa3 : Don't Care 19 25 ...
Page 26
... L L Any State Any State H L Note: 1. After the power-up, when user wants to change MR Set, user must exit from power-down mode and start MR Set before chip enters normal operation mode. AT49LD3200(B) 26 Input Signal RAS CAS MR Add ...
Page 27
... CAS Latency CAS Latency CAS Latency (max (max) has been reached, a new “ACTIVE” command is necessary for RC VCVC AT49LD3200(B) t (min) t (min) RC VCVC ( ( (min) t (min) RC VCVC ( ...
Page 28
... PRE CMD (2) Data(CL2 Data(CL3) Data(CL4) Notes: 1. The data bus goes to high-Z after CAS latency from the Burst Stop (or precharge) command. 2. Valid output data will last up to CL-1 clock cycle from PRE command. AT49LD3200(B) 28 DQB DQB DQB DQB DQB DQB ...
Page 29
... CASE III) ACT RDb DQb DQb 0 1 DQa DQa DQa DQa DQb DQa DQa DQa DQa AT49LD3200(B) CASE II ) CASE III ) RDb DQb DQb DQb DQb DQa DQa DQb DQb DQb DQb DQa ...
Page 30
... MHz CLK CMD ACT RDa CASE I ) CASE II ) CASE III ) @ MHz CLK tVCVC=3 CMD RDa ACT CASE I ) CASE II ) CASE III ) AT49LD3200(B) 30 VCVC tVCVC=5 CASE I) RDb CASE II) RDb CASE III) RDb DQb DQa DQa DQa DQa 0 1 ...
Page 31
... DQM High to Output Float DF t Output Hold from Address OH AC Waveforms for Boot Block Read Operation ADDRESS OUTPUT 1940B–FLASH–11/01 Condition CS = DQM = ADDRESS VALID DQM t ACC HIGH-Z AT49LD3200(B) Min Max 170 OUTPUT VALID Units ...
Page 32
... L) will be treated as NOP, and the number of clock cycles between the bus cycle and the Precharge command or vice versa should be “Don’t Care”. 2. For boot block programming ing the four-bus cycle command operation. 3. For boot block erasing DQM should be held “H” during the six-bus cycle command operation. AT49LD3200( PROGRAM CYCLE 55 ...
Page 33
... After Program cycle, DATA = same state as loaded DQ7. During Sector Erase cycle, DATA = “0”; after Sector Erase cycle, DATA = “1”. 1940B–FLASH–11/ PGM READ (DATA POLLING) DATA t /t PGM EC READ (DATA POLLING) DATA AT49LD3200(B) CA READ DATA READ DATA 33 ...
Page 34
... Note: For x16 Mode, Manufacturer Code 001F(HEX), Device Code 32C2 (HEX). For x32 Mode, Code 32C2001F (HEX). Continuity Test Mode Entry Waveforms CLK DQM CS WE RAS CAS AA 55 ADDR PRECHARGE AA DATA AT49LD3200(B) 34 PRODUCT ID CYCLE PRECHARGE COMMAND COMMAND ...
Page 35
... BOOT BLOCK LOCKOUT CYCLE PRECHARGE PRECHARGE COMMAND COMMAND 80 55 BOOT BLOCK LOCKOUT VERIFY CYCLE PRECHARGE PRECHARGE PRECHARGE COMMAND COMMAND COMMAND 80 AA AT49LD3200(B) t BBL PRECHARGE PRECHARGE COMMAND COMMAND AA 40 200 PRECHARGE COMMAND 90 READ DQ 35 ...
Page 36
... Boot Block Lockout Verify Exit Cycle Waveforms CLK CS WE RAS CAS AA 55 ADDR 55 PRECHARGE COMMAND AA DATA AT49LD3200(B) 36 BOOT BLOCK LOCKOUT VERIFY EXIT CYCLE PRECHARGE PRECHARGE PRECHARGE COMMAND COMMAND µ PRECHARGE COMMAND COMMAND F0 1940B–FLASH–11/01 ...
Page 37
... Thin Small Outline Package (TSOP Type II) 1940B–FLASH–11/01 Ordering Code Package AT49LD3200-10TC AT49LD3200-10TI AT49LD3200-13TC AT49LD3200-13TI AT49LD3200-20TC AT49LD3200-20TI Package Type AT49LD3200(B) Operation Range 86T Commercial (0° to 70°C) 86T Industrial (-40° to 85°C) 86T Commercial (0° to 70°C) ...
Page 38
... This package conforms to JEDEC reference MO-142, Variation EC. 2. Dimensions D and E1 do not include mold protrusion. Allowable protrusion 0.25 mm per side and 0.15 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LD3200( TITLE 86T, 86-lead (10 ...
Page 39
... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...