at49ld3200 ATMEL Corporation, at49ld3200 Datasheet - Page 11

• Manufacturer Part Number: at49ld3200
• Description: At49ld3200 32-megabit 1m X 32 Or 2m X 16 High-speed Synchronous Flash Memory
• Manufacturer: ATMEL Corporation

Burst Sequence (Burst Length = 4)
Burst Sequence (Burst Length = 8)
Device Operations
Clock (CLK)
Clock Enable (CKE)
NOP and Device
Deselect
1940B–FLASH–11/01
A2
0
0
0
0
1
1
1
1
A1
Initial Address
0
0
1
1
Initial Address
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
0
1
2
3
0
1
2
3
4
5
6
7
A square wave signal (CLK) must be applied externally at cycle time t
are synchronized to the rising edge of the clock. The clock transitions must be mono-
tonic between V
in valid state (low or high) for the duration of setup and hold time around the positive
edge of the clock for proper functionality and I
The clock enable (CKE) gates the clock into the AT49LD3200(B) and is asserted high
during all cycles, except for power-down, standby and clock suspend mode. If CKE goes
low synchronously with clock (setup and hold time same as other inputs), the internal
clock is suspended from the next clock cycle and the state of output and burst address
is frozen for as long as the CKE remains low. All other inputs are ignored from the next
clock cycle after CKE goes low. The AT49LD3200(B) remains in the power-down mode,
ignoring other inputs for as long as CKE remains low. The power-down exit is synchro-
nous as the internal clock is suspended. When CKE goes high at least “1 CLK + t
before the rising edge of the clock, then the AT49LD3200 becomes active from the
same clock edge accepting all the input commands.
When RAS, CAS and MR are high, the AT49LD3200(B) performs no operation (NOP).
NOP does not initiate any new operation. Device deselect is also a NOP and is entered
by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR
1
2
3
4
5
6
7
0
1
2
3
0
Sequential
2
3
4
5
6
7
0
1
Sequential
3
4
5
6
7
0
1
2
IL
and V
2
3
0
1
4
5
6
7
0
1
2
3
IH
. During operation with CKE high, all inputs are assumed to be
5
6
7
0
1
2
3
4
3
0
1
2
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
CC
specifications.
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
1
0
3
2
AT49LD3200(B)
Interleave
Interleave
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
2
3
0
1
CC
. All operations
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
SS
11
”