z89176 ZiLOG Semiconductor, z89176 Datasheet - Page 44
z89176
Manufacturer Part Number
z89176
Description
Voice Processing Controllers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z89176.pdf
(68 pages)
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Z8
Z89175/Z89176
Voice Processing Controllers
WDT Time Select (D0, D1). These bits selects the WDT
time period. The configuration is shown in Table 10.
Notes:
TpC = XTAL clock cycle.
Tolerance = 10%
44
®
D1
0
0
1
1
/RESET
FUNCTIONAL DESCRIPTION (Continued)
Select (SMR)
WDT Select
CK Source
Stop Delay
(WDTMR)
From Stop
(WDTMR)
Recovery
D0‘
2V REF .
0
1
0
1
Source
Table 10. WDT Time Select
Select
XTAL
Mode
VDD
WDT
Internal RC OSC
12 ns Glitch Filter
Time-out of
100 ms min
15 ms min
25 ms min
5 ms min
+
-
4 Clock
Filter
RC
OSC.
2V Operating
Voltage Det.
XTAL Clock
Time-out of
1024 TpC
4096 TpC
256 TpC
512 TpC
M
U
X
Figure 30. Resets and WDT
P R E L I M I N A R Y
Clear
CLK
CK
5 ms POR
CLR
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT mode. A 1 indicates ac-
tive during HALT. The default is 1.
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP mode. Since XTAL
clock is stopped during STOP mode, the on-board RC
must be selected as the clock source to the POR counter.
A 1 indicates active during STOP. The default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0 which selects the RC oscillator.
18 Clock RESET
WDT/POR Counter Chain
5 ms 15 ms 25 ms 100 ms
Generator
WDT TAP SELECT
RESET
DS97TAD0100
Internal
RESET
Zilog
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