z89176 ZiLOG Semiconductor, z89176 Datasheet - Page 41

• Manufacturer Part Number: z89176
• Description: Voice Processing Controllers
• Manufacturer: ZiLOG Semiconductor

Zilog
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
DS97TAD0100
D4
SMR D4 D3 D2
0
0
0
0
1
1
1
1
Stop Mode Recovery Edge
Select (SMR)
P33 From Pads
Digital/Analog Mode
Select (P3M)
Table 8. Stop-Mode Recovery Source
0
SMR:432
VDD
0
D3
0
0
1
1
0
0
1
1
P31
P32
0
SMR
D2
0
1
0
1
0
1
0
1
D4 D3 D2
0
0
1
1
P33
POR and/or external reset
recovery
No effect
P31 transition
P32 transition
P33 transition
HSEC
Logical NOR of P20 through
P23
Logical NOR of P20 through
P27
0
1
Description of Action
SMR
Operation
D4 D3 D2
1
Figure 27. Stop-Mode Recovery Source
0
HSEC
0
SMR
P R E L I M I N A R Y
D4 D3 D2
1
0
P20
P23
1
control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the STOP re-
covery (Figure 27 and Table 8).
Stop-Mode Recovery Delay Select (D5). When Low, this
bit disables the 5 ms /RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the “fast”
wake up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89175/176 from STOP mode. A 0 in-
dicates low level recovery. The default is 0 on POR (Table
8).
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read-Only. It is used to
distinguish between a cold or warm start.
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can con-
figure the internal system clock (SCLK) or the Z8, /RE-
SET, and HALT of the DSP, and control the interrupt inter-
face between the Z8 and the DSP (Table 9).
SMR
D4 D3 D2
1
1
P20
P27
0
Voice Processing Controllers
SMR
MUX
D4 D3 D2
1
1
1
T o P33 Data
Latch and IRQ1
Z89175/Z89176
T o POR
RESET
41
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