z89176 ZiLOG Semiconductor, z89176 Datasheet
z89176
Related parts for z89176
z89176 Summary of contents
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... Two DSP Timers to Support Different A/D and D/A Sampling Rates IBM Developer’s Toolbox for T.A.M. Applications The Z89176 is the ROMless version of the Z89175. How- ever, the on-chip DSP is not ROMless. Notes: All Signals with a preceding front slash, "/", are ac- tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only) ...
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... Z89175/Z89176 Voice Processing Controllers GENERAL DESCRIPTION (Continued) Z8 Core Processor The on-chip Z8 is Zilog’s 8-bit microcontroller core with an Expanded Register File to allow access to register- mapped peripheral and I/O circuits. The Z8 offers a flexible I/O scheme, an efficient register and address space struc- ture and a number of ancillary features which makes it ide- ally suited for high-volume processing, peripheral control- lers and consumer applications ...
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... RAM 0 Internal Address Bus 8K Words Program DSP Core ROM Internal Data Bus INT 1 INT 2 Extended Bus of the DSP Timer 2 Timer Z89175/Z89176 Voice Processing Controllers P31 P32 P33 Port 3 P34 Output P35 P36 P37 P40 P41 ...
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... Z89175/Z89176 Voice Processing Controllers PIN DESCRIPTION (Continued P06 P05 P04 P03 85 P02 P01 P00 GND P17 90 P16 P15 P14 P13 P12 95 P11 P10 GND AGND VREF- 100 ANIN 1 Figure 2. Z89175 100-Pin QFP Pin Configuration 100-Pin QFP 5 10 ...
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... Port 5, Bit 0-1 No Connection Input Crystal Input (32.768 kHz) Output Crystal Output (32.768 kHz) No Connection No Connection Input/Output Port 0, Bit 7-0 Input/Output Port 1, Bit 7-0 Analog GND Input Analog Voltage Ref- Input Analog Input Z89175/Z89176 Voice Processing Controllers Function = + ...
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... Z89175/Z89176 Voice Processing Controllers PIN DESCRIPTION (Continued P07 P06 P05 80 P04 P03 P02 P01 P00 85 GND P17 P16 P15 P14 P13 90 P12 P11 P10 GND AGND 95 VREF- ANIN VREF+ ANVDD 100 1 Figure 3. Z89175 100-Pin VQFP Pin Configuration 6 70 ...
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... Input/Output Input/Output Input/Output Input/Output Input Output Input/Output Input/Output Input Input Z89175/Z89176 Voice Processing Controllers Symbol Digital Ground Digital VCC = +5V Analog Voltage Ref+ Analog VDD PWM Output Control Input DSP User Output 1, 0 Address Strobe Data Strobe ...
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... P02 P01 P00 GND P17 90 P16 P15 P14 P13 P12 95 P11 P10 GND AGND VREF- 100 ANIN 1 Figure 4. Z89176 100-Pin QFP Pin Configuration 100-Pin QFP VCC P51 ...
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... Zilog Table 3. Z89176 100-Pin QFP Pin Identification I/O Port Symbol Pin Number GND 3, 53, 88 16, 47 VREF+ 1 ANV 2 DD PWM 4 DSP1 /AS 8 /DS 9 R// P57-P54 12-15 XTAL2 17 XTAL1 18 P53-P52 19, 20 P37-P34 21-24 P33-P31 25-27 /RESET 28 P20-P27 29-36 P40-P47 37-44 P50-P51 45 48-52 OSC1 54 OSC2 ...
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... P00 85 GND P17 P16 P15 P14 P13 90 P12 P11 P10 GND AGND 95 VREF- ANIN VREF+ ANVDD 100 1 Figure 5. Z89176 100-Pin VQFP Pin Configuration 100-Pin VQFP VCC ...
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... Zilog Table 4. Z89176 100-Pin VQFP Pin Identification I/O Port Symbol Pin Number GND 1, 51, 86 14, 45 VREF+ 99 ANV 100 DD PWM 2 DSP1 /AS 6 /DS 7 R// P57-P54 10-13 XTAL2 15 XTAL1 16 P53-P52 17, 18 P37-P34 19-22 P33-P31 23-25 /RESET 26 P20-P27 27-34 P40-P47 35-42 P50-P51 43 46-50 OSC1 52 OSC2 ...
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... Z89175/Z89176 Voice Processing Controllers ABSOLUTE MAXIMUM RATINGS Sym Description Min V Supply –0.3 CC Voltage (*) T Storage Temp –65 STG T Oper. A Ambient Temp. Notes: *Voltage on all pins with respect to GND. †See Ordering Information. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted ...
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... CC CC 5.0V GND –0.3 0 5.0V V –0.4 CC 5.0V 0.4 5.0V 1.2 5. 5.0V GND –0.3 5.0V 5.0V –10 5.0V –10 5. Z89175/Z89176 Voice Processing Controllers Typical @ 25 C Units Conditions See Note 2 2.5 V Driven by External Clock Generator 1.5 V Driven by External Clock Generator 2.5 V 1 –2 ...
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... Z89175/Z89176 Voice Processing Controllers DC ELECTRICAL CHARACTERISTICS Z89175 A/D Converter V Sym Parameter I Input Leakage 5.5V IL Analog Input I Input Leakage 5.5V IH Analog Input I Input Current 5.5V VREFH I Input Current 5.5V VREFL I Input Current 5.5V VEFL I Input Current 5.5V VREFL + Min Max Units DD 1.00 2.00 1. –2. ...
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... Input Current IL P31, P32, P33 DS97TAD0100 + Min Max DD 5.5V 6.00 5.5V 6.00 5.5V 1.00 5.5V 1.00 5.5V 1.00 5.5V 30 5.5V 30 5.5V 1.20 5.5V 0.60 5.5V 4.00 5.5V 4.00 5.5V 1.00 5.5V 1. Z89175/Z89176 Voice Processing Controllers Units Conditions ...
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... Z89175/Z89176 Voice Processing Controllers AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram R//W 12 Port 0, /DM 19 Port 1 1 /AS 4 /DS (Read) Port1 /DS (Write) Figure 7. External I/O or Memory Read/Write Timing ...
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... All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. DS97TAD0100 + Note 4 Min 5.0V 25 5.0V 35 5.0V 5.0V 35 5.0V 0 5.0V 125 5.0V 75 5.0V 5.0V 0 5.0V 40 5.0V 35 5.0V 25 5.0V 35 5.0V 40 5.0V 25 5.0V 5.0V 48 5. Z89175/Z89176 Voice Processing Controllers Max Units Notes ns 2,3 ns 2,3 150 ns 1,2 1,2,3 ns 1,2 1,2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 180 ns 1,2,3 ns 2,3 ns 1,2,3 ns 2,3 ...
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... Z89175/Z89176 Voice Processing Controllers AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram Clock 7 7 TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source Figure 8. Additional Timing Zilog DS97TAD0100 ...
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... Z89175/Z89176 Voice Processing Controllers Units Notes [4] 19 ...
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... Z89175/Z89176 Voice Processing Controllers AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In 1 /DAV (Input) RDY (Output) Data Out 7 /DAV (Output) RDY (Input) 20 Data In Valid 2 3 Delayed DAV 4 Figure 9. Input Handshake Timing Data Out Valid Figure 10. Output Handshake Timing ...
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... RDY Fall to DAV Rise Delay 10 TwRDY RDY Width 11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay Note: 5.0V 0.5V DS97TAD0100 V CC Parameter Note 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5.0V 5. Z89175/Z89176 Voice Processing Controllers +70 C Data A Min Max Units Direction TpC ns OUT 0 ...
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... Z89175/Z89176 Voice Processing Controllers PIN FUNCTIONS /RESET (input, active Low). This pin initializes the MCU. Reset is accomplished either through Power-On Reset (POR), Watch-Dog Timer (WDT) reset, Stop-Mode Recov- ery, or external reset. During POR and WDT Reset, the in- ternally generated reset signal is driving the reset pin Low for the POR time ...
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... Port 1 and the control sig- nals /AS, /DS, and R//W (Figure 11). 4 Port 0 (I/O or A15 - A8) 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) 2.3V Hysteresis R = 500 K Figure 11. Port 0 Configuration Z89175/Z89176 Voice Processing Controllers Pad Auto Latch 23 2 ...
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... Z89175/Z89176 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 8-bit, bidirectional, CMOS compatible port (Figure 12). It has multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines are programmed as inputs or outputs, or can be configured un- der software control as an Address/Data port for interfac- ing external memory ...
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... Port 2 (I/O) Z89175/176 MCU 1.5 2.3V Hysteresis R = 500 K Figure 13. Port 2 Configuration Z89175/Z89176 Voice Processing Controllers Handshake Controls /DAV2 and RDY2 (P31 and P36) Auto Latch 2 Pad 25 ...
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... Z89175/Z89176 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 3 (P37-P31). Port 7-bit, CMOS compatible port with three fixed inputs (P33-P31) and four fixed outputs (P37-P34 configured under software control for in- put/output, counter/timers, interrupt, and port handshakes. Pins P31, P32, and P33 are standard CMOS inputs; out- puts are push-pull ...
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... Recovery Source DS97TAD0100 MCU R247 = P3M DIG Figure 14. Port 3 Configuration Z89175/Z89176 Voice Processing Controllers Port 3 (I/O or Control Analog Digital IRQ2 P31 Data IN Latch IRQ0, P32 Data Latch IRQ1, P33 Data Latch 2 27 ...
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... Z89175/Z89176 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 4 (P47-P40). Port 8-bit, bidirectional, CMOS compatible I/O port (Figure 15). These eight I/O lines are configured under software control independently as inputs or outputs. Port 4 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain ...
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... Whether this level cannot be determined. A valid CMOS level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. Port 5 Z89175/176 (I/O) MCU 2.3V Hysteresis R = 500 K Figure 16. Port 5 Configuration Z89175/Z89176 Voice Processing Controllers Pad Auto Latch 29 2 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION The Z8 core of the Z89175/176 incorporates special func- tions to enhance the Z8’s application in a variety of voice- processing applications. Reset. The device is reset in one of the following condi- tions: Power-On Reset Watch-Dog Timer Stop-Mode Recovery Source External Reset Program Memory ...
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... An LDC opcode references PROGRAM (/DM inactive) DS97TAD0100 memory, and an LDE instruction references data (/DM ac- tive Low) memory. 65535 24575 0 Figure 18. Data Memory Map Z89175/Z89176 Voice Processing Controllers External Data Memory Not Addressable (In ROM Mode ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) ® Register File. The standard Z8 register file consists of four I/O port registers, 236 general-purpose registers, and 15 control and status registers (R0-R3, R4-R239, and R241-R255, respectively). The instructions access regis- ters directly or indirectly through an 8-bit address field. ...
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... Group 13 (D) Group 4 (4) Specified Working Group 3 (3) Register Group Group 2 (2) Group 1 (1) Group 0 (0) I/O Ports Figure 20. Register Pointer Z89175/Z89176 Voice Processing Controllers R255 R253 R240 R239 R223 R79 The upper nibble of the register file address ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) REGISTER POINTER Working Register Expanded Register Group Pointer Bank Pointer Z8 Reg. File FFH FOH 7FH 0FH 0 00H Notes Unknown † = For ROMless mode, RESET Condition 10110110 Will not be Reset with a Stop-Mode Recovery * Figure 21 ...
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... Mask Register globally or individually enables or dis- ables the six interrupt requests. IRQ0 IRQ2 IRQ1 Interrupt Edge Select IRQ IMR IPR Global Interrupt Enable Priority Logic Vector Select Figure 22. Interrupt Block Diagram Z89175/Z89176 Voice Processing Controllers IRQ Register (D6, D7 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) Table 6. Interrupt Types, Sources, and Vectors Vector Name Source Location IRQ0 /DAV0, P32 AN2 IRQ1 /DAV1, P33 2, 3 IRQ2 /DAV2, P31 TIN, AN2 IRQ3 IRQ3 6, 7 IRQ4 IRQ5 TI 10, 11 When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder controlled by the Interrupt Priority Register ...
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... The counter/timers can be cascaded by connecting the T0 output to the input of T1 Z89175/Z89176 Voice Processing Controllers XTAL1 XTAL2 External Clock 37 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) DSP Clock 2 D7, D6 (F) OC (DSP CON) 2 D0,D1 (SMR) 16 Internal Clock External Clock Clock Logic 4 Internal Clock Gated Clock Triggered Clock TIN P31 38 2 OSC T0, T2, T3 Write Write PRE0 Initial Value Register 6-Bit 4 Down Counter ...
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... To do this, the user must execute a NOP (opcode=FFH) immediately before the appropriate Sleep instruction, i.e., FF NOP 6F STOP FF NOP 7F HALT Z89175/Z89176 Voice Processing Controllers ; clear the pipeline ; enter Stop mode or ; clear the pipeline ; enter Halt mode 39 2 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) Stop-Mode Recovery Register (SMR). This register se- lects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 26). All bits are Write-Only except bit 7, which is Read-Only. Bit flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle ...
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... Z8 and the DSP. It can con- figure the internal system clock (SCLK) or the Z8, /RE- SET, and HALT of the DSP, and control the interrupt inter- face between the Z8 and the DSP (Table 9 Z89175/Z89176 Voice Processing Controllers SMR ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) Table 9. DSP Control Register (F) OCH [Read/Write] Field DSPCON (F)0CH Position Z8_SCLK 76------ DSP_Reset --5----- DSP_Run ---4---- Reserved ----32-- DSP_INT2 ------1- Z8_IRQ3 -------0 Z8 IRQ3 (D0). When read, this bit indicates the status of the Z8 IRQ3. The Z8 IRQ3 is set by the DSP by writing DSP External Register 4 (ICR) ...
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... XTAL W No effect R Always "1" Figure 28. Watch-Dog Timer Mode Register HSEC ( Figure 29. Half-Second Timer Status Register Z89175/Z89176 Voice Processing Controllers INT RC OSC EXTERNAL CLOCK 5 ms 256 Tpc 15 ms 512 Tpc ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 FUNCTIONAL DESCRIPTION (Continued) WDT Time Select (D0, D1). These bits selects the WDT time period. The configuration is shown in Table 10. Table 10. WDT Time Select Time-out of D1 D0‘ Internal RC OSC min min min ...
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... To receive information from the DSP, the Z8 uses eight in- coming registers which are mapped in the Z8 extended Register File (Bank 0F). The DSP treats these as four 16-bit registers that correspond to the eight incoming Z8 registers (Figure 32 Z89175/Z89176 Voice Processing Controllers Register Definition 2 45 ...
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... Z89175/Z89176 Voice Processing Controllers DSP REGISTERS DESCRIPTION (Continued) The Z8 can supply the DSP with data through eight outgo- ing registers mapped into both the Z8 Expanded Register File (Bank B, Registers 00 to 07) and the external register interface of the DSP. These registers are Read/Write and can be used as general-purpose registers of the Z8 ...
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... Table 14. DSP Incoming Registers Attrib Z89175/Z89176 Voice Processing Controllers Value Label %NN DSP_ext0_hi No Effect %NN DSP_ext0_lo No Effect %NN DSP_ext1_hi No Effect %NN DSP_ext1_lo No Effect %NN DSP_ext2_hi No Effect %NN DSP_ext2_lo No Effect %NN DSP_ext3_hi No Effect ...
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... Z89175/Z89176 Voice Processing Controllers DSP Interrupts The DSP processor has three interrupt sources (INT2, INT1, INT0) (Figure 33). These sources have different pri- ority levels (Figure 34). The highest priority, the next lower and the lowest priority level are assigned to INT2, INT1 Z8_INT ...
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... Attrib R/W R/W R R/W R/W R/W R Z89175/Z89176 Voice Processing Controllers DSP Side DSP INT2 After serving INT2, set D4 to clear the interrupt request. ICR 4 (EXT4) The DSP sets D9 to interrupt Z8 via Z8 IRQ3. Value Label 1 Set_IRQ2 0 Reset_IRQ2 ...
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... Z89175/Z89176 Voice Processing Controllers DSP REGISTERS DESCRIPTION (Continued) Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition Field Position -----------4---- Clear_IRQ1 ------------3--- ------------3--- Clear_IRQ0 -------------2-- -------------2-- Reserved --------------10 Interrupt Control Register (ICR). The ICR is mapped into EXT4 of the DSP (Table 15). The bits are defined as fol- lows: DSP_IRQ2 (Z8 Interrupt) ...
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... R/W 1 P26 0 Timer3 R Return “0” effect R Return “1” effect R Z89175/Z89176 Voice Processing Controllers Reserved 10-Bit Data for D/A (Write Only) Reserved 1 0 Reserved 8-Bit Data From A/D Converter (Read Only) Reserved 20.48 Label MHz 16 kHz 8 ...
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... Z89175/Z89176 Voice Processing Controllers DSP REGISTERS DESCRIPTION (Continued) Table 17. EXT6 Analog Control Register (ACR) Field Position DSP_port (DSP1, --------76------ DSP0) Enable A/D ----------5----- ConversionDone -----------4---- StartConversion ------------3--- Reserved -------------2-- 20/29 MHz Select --------------1- A/D_SamplingRate---------------0 Notes: * Default value † Optional feature DSP IRQ0. This bit defines the source of the DSP IRQ0 in- terrupt ...
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... Timer2 8, 16 kHz OSC 20.48 MHz Timer3 16, 10 kHz Timer2 16, 9.6 kHz USC 29.49 MHz Timer3 8.04, 9.6 kHz Figure 37. Timer2 and Timer3 Z89175/Z89176 Voice Processing Controllers Table 19. A/D Sampling Rate Sampling Rate Bit 0 20.48 MHz 29.49 MHz 1 16 kHz 0 8 kHz A/D D/A A/D D/A ...
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... Z89175/Z89176 Voice Processing Controllers Pulse Width Modulator (PWM) The PWM supports two different sampling rates (10 and 16 kHz), according to the settings of bit 8 of the ACR. The out- put of the PWM can be assigned to logic 1 only during the active region (which is 4/5 of the output signal period). The output will be at logic 0 for the rest of the time ...
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... Zilog Figure 39. PWM Waveform of the Active Region DS97TAD0100 (for a 6-bit PWM data Z89175/Z89176 Voice Processing Controllers 55 2 ...
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... Z89175/Z89176 Voice Processing Controllers A/D CONVERTER (ADC) Analog to Digital Converter The A/D converter is an 8-bit half flash converter which uses two reference resistor ladders for its upper four bits (MSBs) and lower four bits (LSBs) conversion (Figure 41). Two reference voltage pins, VREF+ (High) and VREF- (Low), are provided for external reference voltage sup- plies ...
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... V is set using the V REF CMOS Switch on Resistance Ref Ref Ref Figure 42. Input Impedance of ADC Z89175/Z89176 Voice Processing Controllers pin. REF 31 CMOS Digital Comparators 2 57 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 EXPANDED REGISTER FILE REGISTERS Expanded Register Bank B ( Figure 43. Outgoing Register to DSP EXT0 (High Byte) (B) 00H [Read/Write] ( Figure 44. Outgoing Register to DSP EXT0 (Low Byte) (B) 01H [Read/Write] ( Figure 45 ...
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... Figure 56. Incoming Register from DSP EXT2 ( DSP EXT1, Bits D15-D8 Figure 57. Incoming Register from DSP EXT3 Z89175/Z89176 Voice Processing Controllers DSP EXT1, Bits D7-D0 (Low Byte) (B) 0BH [Read-Only] DSP EXT2, Bits D15-D8 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 EXPANDED REGISTER FILE REGISTERS (Continued) ( Figure 58. Incoming Register from DSP EXT3 (Low Byte) (B) 0FH [Read-Only] Expanded Register Bank F PCON (F) % Always "1" P34,P37 Standard output R Always " ...
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... P2 NOR 0-7 R Always "1" W Stop Delay 0 OFF 1 ON* R Always "1" Low Stop Recovery Level* 1 High Stop Recovery Level R Always "1" effect R 0 POR* 1 Stop-Mode Recovery (F) 0BH [Read/Write Z89175/Z89176 Voice Processing Controllers 61 2 ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 EXPANDED REGISTER FILE REGISTERS (Continued) Table 20. DSP Control Register (F) 0CH [Read/Write] Field DSPCON (F) 0CH Position Z8_SCLK 76------ DSP_Reset --5----- DSP_Run ---4---- Reserved ----32-- IntFeedback ------1- -------0 WDTMR ( Default setting after RESET 62 Attributes R R WDT TAP ...
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... Internal Clock Out (P36) R243 PRE1 Low Byte Initial Value (When Written) T1 Low Byte Current Value (When Read Z89175/Z89176 Voice Processing Controllers Count Mode 0 T1 Single Pass 1 T1 Modulo N Clock Source 1 T1Internal 0 T1External Timing Input ...
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... Z89175/Z89176 Voice Processing Controllers ® Z8 CONTROL REGISTERS (Continued) R246 P2M Default Setting After Reset Figure 73. Port 2 Mode Register (F6H: Write-Only) R247 P3M Port 2 Pull-Ups Open Drain 1 Port 2 Pull-Ups Active 0 P31, P32 Digital Mode ...
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... User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Z89175/Z89176 Voice Processing Controllers Expanded Register File Bank Working Register Group Figure 80. Register Pointer (FDH: Read/Write) Stack Pointer Upper Byte (SP8 - SP15) Figure 81 ...
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... Z89175/Z89176 Voice Processing Controllers PACKAGE INFORMATION 66 Figure 83. 100-Pin QFP Package Diagram Zilog DS97TAD0100 ...
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... Zilog DS97TAD0100 Figure 84. 100-Pin VQFP Package Diagram Z89175/Z89176 Voice Processing Controllers 67 2 ...
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... Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 68 Z89175 (29 MHz) 100-Pin QFP 100-Pin VQFP Z8917529FSC Z8917529ASC Z89176 (29 MHz) 100-Pin QFP 100-Pin VQFP Z8917629FSC Z8917629ASC Speeds 20 = 20.48 MHz 29 = 29.49 MHz Environmental C = Plastic Standard is a Z89175, 20 ...