z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 47

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Zilog
Field
DSP_IRQ2
DSP_IRQ1
DSP_IRQ0
DSP_MaskINT2
DSP_MaskINT1
DSP_MaskINT0
Z8_IRQ3
DSPintEnable
DSP_IPR2
DSP_IPR1
DSP_IPR0
Clear_IRQ2
Clear_IRQ1
Clear_IRQ0
Reserved
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 13). The bits are defined as fol-
lows:
DSP_IRQ2 (Z8 Interrupt). This bit can be read by both Z8
and DSP and can be set only by writing to the Z8 expand-
ed Register File (Bank F, ROC, bit 0). This bit asserts IRQ2
of the DSP and can be cleared by writing to the
Clear_IRQ2 bit.
DSP_IRQ1 (A/D Interrupt). This bit can be read by the
DSP only and is set when valid data is present at the A/D
DS97TAD0300
f---------------
f---------------
-e--------------
-e--------------
--d-------------
--d-------------
---c------------
----b-----------
-----a----------
------9---------
------9---------
-------8--------
--------7-------
---------6------
----------5-----
-----------4----
-----------4----
------------3---
------------3---
-------------2--
-------------2--
--------------10
Table 13.
Position
EXT4 DSP Interrupt Control Register (ICR) Definition
P R E L I M I N A R Y
Attrib
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
output register (conversion done). This bit asserts IRQ1 of
the DSP and can be cleared by writing to the
Clear_IRQ1bit.
DSP_IRQ0 (D/A Interrupt). This bit can be read by DSP
only and is set by Timer3. This bit assists IRQ0 of the DSP
and can be cleared by writing to the Clear_IRQ0 bit.
DSP_MaskIntX. These bits can be accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks the corresponding INT
off.
Binary
Binary
Binary
Value
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Low-Cost DTAD Controller
Z89135/136 (ROMless)
Label
Set_IRQ2
Reset_IRQ2
No effect
Set_IRQ1
Reset_IRQ1
No effect
Set_IRQ0
Reset_IRQ0
No effect
Enable_INT2
Disable_INT2
Enable_INT1
Disable_INT1
Enable_INT0
Disable_INT0
Return "0"
Set_Z8_IRQ3
Reset_Z8_IRQ3
Enable
Disable
IPR2
IPR1
IPR0
Return "0"
Clear_IRQ2
Has_no_effect
Return "0"
Clear_IRQ1
No effect
Return "0"
Clear_IRQ0
No effect
No effect "0"
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