z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 38

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

FUNCTIONAL DESCRIPTION (Continued)
Z89135/136 (ROMless)
Low-Cost DTAD Controller
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 26). All bits are Write Only,
except bit 7 which is Read Only. Bit 7 is a flag bit that is
hardware set on the condition of Stop recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
a high level is required from the recovery source. Bit 5 con-
1-38
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
*
† Reset After Stop-Mode Recovery
Default Setting After Reset
Figure 26. Stop-Mode Recovery Register (SMR)
P R E L I M I N A R Y
trols the reset delay after recovery. Bits 2, 3, and 4, or the
SMR register, specify the source of the Stop-Mode Recov-
ery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR is located in Bank F of the Expanded Reg-
ister Group at address 0BH.
W 000 POR only*
R
W 0 Stop delay on*
R Always "1"
W 0 Low Stop Recovery Level*
R Always "1"
W No effect
R 0 POR*
W 00 SCLK/TCLK Not Divide by 16†
R Always "1"
1 Stop-Mode Recovery
01 SCLK/TCLK Not Divide by 16
10 SCLK/TCLK Divide by 16
11 SCLK/TCLK Divide by 16
1 Stop delay off
1 High Stop Recovery Level
Always "1"
001 No effect
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
DS97TAD0300
Zilog