z89136 ZiLOG Semiconductor, z89136 Datasheet - Page 46

• Manufacturer Part Number: z89136
• Description: Low-cost Dtad Controller
• Manufacturer: ZiLOG Semiconductor

Z89135/136 (ROMless)
Low-Cost DTAD Controller
DSP INTERRUPTS
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 31). These sources have different pri-
ority levels (Figure 32). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
and INT0, respectively. The DSP does not allow interrupt
nesting (interrupting service routines that are currently be-
1-46
interrupt DSP via DSP INT2.
After serving IRQ3,
set D0 to clear the
interrupt request.
On the Z8, set D1 to
Z8 Side
DSP CON
A/D INT
D/A INT
FB DSP
Z8_INT
IPR2
IPR1
IPR0
IRQ3 of the Z8
DSP Execution
Interrupt Priority Logic
FeedBack Z8_INT MPX
Figure 33. Interprocessor Interrupts Structure
INT0
INT1
INT2
Figure 32. DSP Interrupt Priority Structure
Figure 31. DSP Interrupts
P R E L I M I N A R Y
INT2
Interrupt Request Logic
9
INT0
ing executed). When two interrupt requests occur simulta-
neously the DSP starts servicing the interrupt with the
highest priority level. Figure 33 shows the interprocessor
interrupts mechanism.
1
0
INT1
INT2
INT1
INT0
INT2
CLEAR_INT0
CLEAR_INT1
CLEAR_INT2
ENABLE_INT
4
Interrupt Mask Logic
DSP INT2
interrupt Z8 via Z8 IRQ3.
The DSP sets D9 to
After serving INT2,
set D4 to clear the
interrupt request.
DSP Side
INT2
INT1
INT0
(EXT4)
ICR
DS97TAD0300
Zilog