lm49370rl National Semiconductor Corporation, lm49370rl Datasheet - Page 24

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lm49370rl

Manufacturer Part Number
lm49370rl
Description
Audio Sub-system With An Ultra Low Emi, Spread Spectrum, Class D Loudspeaker Amplifier, A Dual-mode Stereo Headphone Amplifier, And A Dedicated Pcm Interface For Bluetooth Transceivers
Manufacturer
National Semiconductor Corporation
Datasheet

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Bits
7:0
12.6 PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control the feedback divider of the PLL. (Note 13)
The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting
VCO frequency, F
(comparison frequency) or F
The integer division of the N divider is derived from PLL_N such that:
Note 13: See Further Notes on PLL Programming for further details.
PLL_N
Field
VCO
. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as F
This programs the PLL feedback divider as follows:
ref
(reference frequency), in this document F
250 to 255
For 9 < PLL_N < 251: N = PLL_N
PLL_N
0 to 10
249
11
12
13
14
TABLE 7. PLL_N (0x03h)
24
Description
comp
is used.
Feedback Divider Value
249
250
10
11
12
13
14
comp

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