lm49370rl National Semiconductor Corporation, lm49370rl Datasheet - Page 19

• Manufacturer Part Number: lm49370rl
• Description: Audio Sub-system With An Ultra Low Emi, Spread Spectrum, Class D Loudspeaker Amplifier, A Dual-mode Stereo Headphone Amplifier, And A Dedicated Pcm Interface For Bluetooth Transceivers
• Manufacturer: National Semiconductor Corporation

12.1 BASIC CONFIGURATION REGISTER
This register is used to control the basic function of the chip.
Bits
For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by
setting bit 0 of CHIP_MODE:
The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h))
The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))
The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))
The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))
All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered
while the audio sub-system is active.
If the analog or digital levels are below −12dB then it is not necessary to set the stereo bit allowing greater output levels to be
obtained for such signals.
1:0
5:4
7:6
2
3
PLL_ENABLE
CHIP_MODE
DAC_MODE
USE_OSC
CAP_SIZE
Field
The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode
is selected the LM49370 will change operation silently and will re-configure the power management
profile automatically. The modes are described as follows:
This enables the PLL.
If set the power management and control circuits will assume that no external clock is available and
will resort to using an on-chip oscillator for headset detection and analog power management functions
such as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit
must be cleared for the part to be fully turned off power-down mode.
This programs the extra delays required to stabilize once charge/discharge is complete, based on the
size of the bypass capacitor.
The DAC can operate in one of four modes. If an “fs*2
be run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate
a suitable clock.
CHIP MODE
DAC MODE
CAP_SIZE
00
01
10
11
00
01
10
11
00
01
10
11
2
2
2
2
2
2
2
2
2
2
2
2
TABLE 2. BASIC (0x00h)
Bypass Capacitor
Audio System
DAC OSR
0.1 µF
2.2 µF
4.7 µF
1 µF
Size
125
128
Off
Off
On
On
64
32
19
Description
Stand-by mode with headset event detection
Active without headset event detection
N
Active with headset event detection
192kHz Playback from 24.576MHz
” audio clock is available, then the DAC can
96kHz Playback from 12.288MHz
48kHz Playback from
48kHz Playback from
Typical Application
Power-down Mode
Typical Application
Turn-off/on time
45 ms/140 ms
45 ms/260 ms
45 ms/500 ms
45 ms/75 ms
12.000MHz
12.288MHz
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