lm49370rl National Semiconductor Corporation, lm49370rl Datasheet - Page 21

• Manufacturer Part Number: lm49370rl
• Description: Audio Sub-system With An Ultra Low Emi, Spread Spectrum, Class D Loudspeaker Amplifier, A Dual-mode Stereo Headphone Amplifier, And A Dedicated Pcm Interface For Bluetooth Transceivers
• Manufacturer: National Semiconductor Corporation

12.3 LM49370 CLOCK NETWORK
The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as
marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires a 12.000MHz (or 12.288MHz) clock
(at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system operating at 125*fs unless a 12.000 MHz
master clock is supplied or the sample rate is always a multiple of 8 kHz. In this case the PLL can be bypassed to reduce power,
with clock division being performed by the Q and R dividers instead. The PLL can also be bypassed if the system is running at
128*fs and a 12.288MHz master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I
2
S clock
input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL
output divided by 2*F
/F
or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback.
S(DAC)
S(ADC)
MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz.
When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. When operating
at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A. This is used to drive the power
management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates
significantly beyond this range.
20191710
FIGURE 6. LM49370 Clock Network
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