psf21911 ETC-unknow, psf21911 Datasheet - Page 91

• Manufacturer Part Number: psf21911
• Description: Isdn Echocancellation Circuit Terminal Applications Iec-q
• Manufacturer: ETC-unknow

PSB 21911
PSF 21911
S/G Bit and BAC Bit in TE Mode
D-Channel Request by the Terminal
Figure 31 illustrates the request for the HDLC-controller by the terminal. The start state
is BAC = 1 at DIN after TD1 has expired. That causes the S/G bit to be set to the stop
position.
BAC = 1 received on DIN sets the S/G bit on DOUT to the stop position ("1") at the next
IOM-frame. When the terminal requests access to the HDLC-controller in the ELIC it sets
the BAC-bit at DIN of it’s IEC-Q TE to "0". That causes the D-channel data upstream to
be tied to "0" and the S/G-bit to be set to "1". The ELIC receives the zeros and reacts by
assigning the HDLC-controller to this very terminal. This is indicated via the change of C/
I code downstream at the LT side resulting in the S/G bit to be set to "0" (’go’) after delay
TD1 (see below for the explanation of TD1 and TD2).
The IEC-Q TE will continue to send "0" upstream in the D-channel until the actual HDLC
data arrives at DIN.The HDLC-frame itself, marked by the first "0" in the D-channel will
reset the D-channel back to transparent. This allows to have arbitrary delays between
the S/G bit going to "0" and the D-channel being used without the risk of loosing the
HDLC-controller by sending an abort request consisting of all "1".
At the end of the HDLC-frame the BAC bit is reset to "1" again by the layer-2 controller
(e.g. SMARTLINK; ICC). This causes the S/G bit to be set to "1" in the next IOM frame
which stops a possible second HDLC-frame that could not be processed in the ELIC
anymore.
TD1 and TD2
The delays TD1 and TD2 (see figure 31) have the following reasons: TD2 is caused by
the 6ms interval in which an EOC message can be transmitted on the Uko interface. As
an EOC-message can start once every 6 ms and will take 6 ms to be transmitted, TD2
will be 12 ms in the worst case.
TD1 is at minimum 7.5 ms depending on the location of the superframe at the time the
HDLC-controller is requested by the terminal. This delay is necessary because instead
of receiving an EOC-message "go" as requested, the terminal could as well receive the
EOC message "stop" because the HDLC-controller was assigned to an other subscriber
just before .
Flags as interframe Fill
The influence to the upstream D-channel can be disabled while the control of the S/G-
bit via EOC-messages and via the BAC bit still is given as described above by setting
SWST:BS to "0", SWST:SGL to "1" and ADF:CBAC to "1". This is usefull when having a
controlling device in the terminal, that is able to send the interframe timefill "flags".
Semiconductor Group
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