psf21911 ETC-unknow, psf21911 Datasheet - Page 126

• Manufacturer Part Number: psf21911
• Description: Isdn Echocancellation Circuit Terminal Applications Iec-q
• Manufacturer: ETC-unknow

Semiconductor Group
ADF-Register
Additional Features Register (ADF).
Default: 14
7
WTC2, WTC1:
PCL1, PCL0:
Bit 2:
BCL:
CBAC:
WTC2
WTC1
H
PCL1
Watchdog Controller
The bit patterns “10“ and “01“ has to be written in WTC1 and
WTC2 by the enabled watchdog timer within 132ms. If it fails to
do so, a reset signal of 5ms at pin RST is generated.
Prescaler
The clock frequency on MCLK is selected by setting the bits
according to the table below:
Reserved
Set to 0 for future compatibility.
Bit Clock
BCL = 1 changes the DCL-output into the bit-clock-mode.
BCL = 0 gives the doubled bit clock on the DCL-output.
Control BAC
Operates in combination with SWST:SGL and SWST:BS bits to
control the S/G bit and the BAC bit. For the functional description
see Table 18 on page 89.
PCL0
PCL1
0
0
I
I
Write
126
PCL0
0
0
I
I
BCL
CBAC
Register Description
Frequency at
MCLK (MHz)
0
7.68
3.84
1.92
0.96
PSB 21911
PSF 21911
Address E
E
H
11.97
H