psf21911 ETC-unknow, psf21911 Datasheet - Page 114

• Manufacturer Part Number: psf21911
• Description: Isdn Echocancellation Circuit Terminal Applications Iec-q
• Manufacturer: ETC-unknow

PSB 21911
PSF 21911
Register Description
4.1
Interrupt Structure
The cause of an intrerrupt is determinded by reading the Interrupt Status Register
(ISTA). In this register, 7 interrupt sources can be directly read. Interrupt bits are cleared
by reading the corresponding registers. ISTA:D is cleared after DRI and DRU have been
read. ISTA:B1 is cleared after RB1I and RB1U have been read. ISTA:B2 is cleared after
RB2I and RB2U have been read etc. ISTA:CICI is cleared after CIRI is read, ISTA:CICU
is cleared after CIRU is read. ISTA:SF indicates a superframe marker received from the
U-interface. It is cleared when the ISTA register has been read. Pin INT is set to "0" if
one bit of ISTA changes from "0" to "1", except for the bit masked in the MASK register.
The MASK register allows to prevent an interrupt to actually influence the INT pin.
Setting the bits of MASK that correspond to the bits of ISTA to "1" masks the bits, that
is, the bits are still set in ISTA, but they do not contribute to the input of the NOR-function
on the interrupt bits which sets the INT pin. The interrupt structure is illustrated in
figure 46:
Figure 46 Interrupt Structure
Semiconductor Group
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