pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 179

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

4.7.15 Transmit Address Byte 2 (XAD2)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
XAD27..20
4.7.16 Receive Address Byte Low Register 1 (RAL1)
Access in demultiplexed
Access in multiplexed
Reset value: xx
RAL17..10
Note: In auto-mode and non-auto mode the read back of the programmed value is
Semiconductor Group
bit 7
bit 7
P-interface mode:
P-interface mode:
XAD27
RAL17
inverted.
XAD26
RAL16
Transmit Address byte 2.
The value stored in XAD2 is included automatically as the low address
byte of all frames transmitted in auto-mode (2-byte address field only).
Receive Address byte Low register 1.
The general function (read/write) and the meaning or contents of this
register depends on the selected operating mode:
H
H
Auto-mode, non-auto mode (address recognition) - write only:
compare value 1, address recognition (low byte in case of 2-byte
address field).
Transparent mode 1 (high byte address recognition) - read only:
RAL1 contains the byte following the high byte of the address in the
received frame (i.e. the second byte after the opening flag).
Transparent mode 0 (no address recognition) - read only:
contains the first byte after the opening flag (first byte of the received
frame).
Extended transparent mode 0,1 - read only:
RAL1 contains the actual data byte currently assembled at the RxD-pin
by passing the HDLC-receiver (fully transparent reception without
HDLC-framing).
XAD25
RAL15
XAD24
RAL14
read/write
read/write
179
XAD23
RAL13
write
write
address: (Ch-A/Ch-B): 25
address: (Ch-A/Ch-B): 4A
address: (Ch-A/Ch-B): 28
address: (Ch-A/Ch-B): 50
Detailed Register Description
XAD22
RAL12
XAD21
RAL11
PEB 20550
PEF 20550
bit 0
bit 0
XAD20
RAL10
H
H
H
H
/65
/68
/D0
/CA
01.96
H
H
H
H