pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 106

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

3.8
For proper initialization of the ELIC the following procedure is recommended:
3.8.1
A reset pulse can be applied at the RESEX-pin for at least 4 PDC-clock cycles. The reset
pulse sets all registers to their reset values (cf. chapter 4.1).
Note that in this state DCL and FSC do not deliver any clock signals.
3.8.2
As the EPIC-1 forms the core of the ELIC, it should usually be programmed first.
3.8.2.1 Register Initialization
The PCM- and CFI-configuration registers (PMOD, PBNR,
be programmed to the values required for the application. The correct setting of the
PCM- and CFI-registers is important in order to obtain a reference clock (RCL) which is
consistent with the externally applied clock signals.
The state of the operation mode (OMDR:OMS1..0 bits) does not matter for this
programming step.
3.8.2.2 Control Memory Reset
Since the hardware reset does not affect the EPIC-1 memories (Control and Data
Memories), it is mandatory to perform a "software reset" of the CM. The CM-code ’0000’
(unassigned channel) should be written to each location of the CM. The data written to
the CM-data field is then don’t care, e.g. FF
OMDR:OMS1..0 must be to '00'
Semiconductor Group
Initialization Procedure
EPIC
Hardware Reset
PMOD =
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
CTAR
CBSR
CSCR
MADR =
MACR =
Wait for EPIC.STAR:MAC = 0
®
-1 Initialization
=
=
=
=
=
=
=
=
=
=
PCM-mode, timing characteristics, etc.
Number of bits per PCM-frame
PCM-offset downstream
PCM-offset upstream
PCM-timing
CFI-mode, timing characteristics, etc.
CFI-timing
Number of bits per CFI-frame
CFI-offset (time slots)
CFI-offset (bits)
CFI-sub channel positions
FF
70
H
H
B
for this procedure (reset value).
106
H
.
, CMD1, CMD2,
Operational Description
PEB 20550
PEF 20550
) should
01.96