pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 192

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 52
Mode
Basic Access Types
read/write
read/write
virtual
read
read only
read virtual
write
write virtual
read/write
hardware
affected
Special Access Types
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Data Sheet
Registers Access Types
Symbol Description Hardware (HW)
rw
rwv
r
ro
rv
w
wv
rwh
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
Register is used as input for the HW
Physically, there is no new register in
Physically, there is no new register in
the generated register file. The real
readable and writable register resides
in the attached hardware.
Register is written by HW (register
between input and output -> one cycle
delay)
Same as r type register
Physically, there is no new register in
the generated register file. The real
readable register resides in the
attached hardware.
Register is written by software and
affects hardware behavior with every
write by software.
the generated register file. The real
writable register resides in the attached
hardware.
Register can be modified by hardware
and software at the same time. A
priority scheme decides, how the value
changes with simultaneous writes by
hardware and software.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
192
Register DescriptionWander Configuration Register
Description Software (SW)
Register is read and writable by SW
Register is read and writable by SW (same
as rw type register)
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior
Same as r type register
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
Register is writable by SW (same as w type
register)
Register can be modified by HW and SW,
but the priority SW versus HW has to be
specified.
SW can read the register.
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM