pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 155

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Clock Mode Register 1
CMR1
Clock Mode Register 1
Field
DCS
DXJA
DXSS
Data Sheet
Bits
3
1
0
Type
rw
rw
rw
Description
Disable Clock-Switching
In Slave mode (LIM0.MAS = ´0´) the DCO-R is synchronized on the
recovered route clock. In case of loss-of-signal LOS the DCO-R switches
automatically to the clock sourced by port SYNC.
0
1
Disable Internal Transmit Jitter Attenuation
Setting this bit disables the transmit jitter attenuation. Reading the data
out of the transmit elastic buffer and transmitting on XL1/2
(XDOP/N/XOID) is done with the clock provided on pin TCLK. In transmit
elastic buffer bypass mode the transmit clock is taken from FCLKX,
independent of this bit.
DCO-X Synchronization Clock Source
0
1
B
B
B
B
which is sourced by FCLKX/R or RCLK. Since there are many
reference clock opportunities the following internal prioritizing in
descending order from left to right is realized: LIM1.RL >
CMR1.DXSS > LIM2.ELT > current working clock of transmit
system interface. If one of these bits is set the corresponding
reference clock is taken.
multi function port XPA or XPB pin function TCLK, if no remote loop
is active. TCLK is selected by PC(2:1).XPC(3:0) = ´0011B´.
automatic switching from RCLK to SYNC is enabled
automatic switching from RCLK to SYNC is disabled
The DCO-X circuitry synchronizes to the internal reference clock
DCO-X synchronizes to an external reference clock provided on
Offset
xx44
155
H
Register DescriptionClock Mode Register 1
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H