w83627hf-pw Winbond Electronics Corp America, w83627hf-pw Datasheet - Page 87
w83627hf-pw
Manufacturer Part Number
w83627hf-pw
Description
W83627hf/f W83627hg/g Winbond Lpc I/o
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83627HF-PW.pdf
(131 pages)
- Current page: 87 of 131
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CR26 (Default 0b0s000000)
BIT
7
6
5
4
3
2
1
0
SEL4FDD
0: Select two FDD mode.
1: Select four FDD mode.
HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is NRTSA (pin 51). HEFRAS Address and Value
0: Write 87h to the location 2E twice.
1: Write 87h to the location 4Etwice.
LOCKREG
0: Enable R/W Configuration Registers
1: Disable R/W Configuration Registers.
Reserve
DSFDLGRQ
0: Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effec-
tive on selecting IRQ
1: Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
DSPRLGRQ
0: Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
1: Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effec-
tive on selecting IRQ
DSUALGRQ
0: Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on select-
ingIRQ
1: Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on se-
lecting IRQ
DSUBLGRQ
0: Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
1: Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on se-
lecting IRQ
- 83 -
DESCRIPTION
W83627HF/ F/ HG/ G
Publication Release Date: June 09, 2006
Revision 2.27
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