sta381bws STMicroelectronics, sta381bws Datasheet - Page 99

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
The STA381BWS implements an automatic CRC computation for the Biquad and
MDRC/XOver coefficient memory
0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will
be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on
I
(for Biquad ram bank) or the XCGO bits (for MDRC/XOver coefficients) will be set to 1. The
checksum is computed at the processing sample rate if the IR bits equal “01” or “10”,
otherwise the checksum is computed to half of the processing sample rate.
When BCCMP or XCCMP is set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is
continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches
its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.
In case of checksum errors (i.e. the internally computed didn’t match the reference), an
automatic device reset action can be activated. This function is enabled when the BCAUTO
or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare
bits are not set.
The suggested procedure for automatic reset activation is the following:
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The previous example is intended for Biquad CRC bank calculation, but it can be easily
extended to MDRC/XOver CRC computation.
2
C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO
Download set of coefficients (RAM locations 0x00…0x27)
Download externally computed biquad checksum into registers BQCHKR
Enable checksum of biquad coefficients by setting the BCGO bit. The checksum will
start to be automatically computed by the STA381BWS and its value exposed on
registers BQCHECKE. The checksum value is computed and updated.
Enable the checksum comparison by setting the BCCMP bit. The internally computed
checksum will start to be compared with the reference one and the result will be
exposed on the BCRES bit. The following operation will be executed on each audio
frame:
Wait until the the BCRES bit goes to 0, meaning that the checksum result bit has
started to be updated and everything is ok. Time-out of this operation (e.g. >1 ms) will
indicate checksum failure, and the MCU will handle this event
Enable automatic reset of the device in case of checksum error by setting the BCAUTO
bit. The BCRES bit will then be automatically checked by the STA381BWS, on each
audio frame, and reset event will be triggered in case of checksum mismatch.
Periodically check the BC_RES status. A value of 1 indicates a checksum mismatch
has occurred and, therefore, that the device went through a reset cycle.
if ((BQCHKE == BQCHKR))
{
}
else
{
}
BC_RES = 0;// Checksum is ok, reset the error bit
BC_RES = 1;// Checksum error detected, set the error bit
Doc ID 018937 Rev 2
(Table
74). Memory cell contents from address 0x00 to
Register description: New Map
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