sta381bws STMicroelectronics, sta381bws Datasheet - Page 105

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
7.1
7.1.1
Note:
Configuration register A (addr 0x00)
Master clock select
Table 100. Master clock select
The STA381BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
●
●
●
The external clock frequency provided to the XTI pin or BICKI pin (depending on MCS
settings) must be a multiple of the input sample frequency (f
The relationship between the input clock (either XTI or BICKI) and the input sample rate is
determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine
the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
used internally. In
clock source, while XTI is used in all the other cases.
Table 101. Input sampling rates
(*) Clock is BICKI
32, 44.1, 48
88.2, 96
176.4, 192
Input sample
Bit
FDRB
0
1
2
fs (kHz)
D7
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
0
rate
R/W
R/W
R/W
R/W
Reserved
D6
1
1X
00
01
IR
Table 101
RST
64*fs(*)
64*fs(*) 32*fs(*)
64*fs(*) 32*fs(*)
1
1
1
111
Reserved
D5
1
MCS 111 and 110 indicate that BICKI has to be used as the
Doc ID 018937 Rev 2
110
NA
MCS0
MCS1
MCS2
Name
Register description: Sound Terminal compatibility
IR1
D4
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
0
101
NA
NA
Description
Selects the ratio between the input I
frequency and the input clock.
64 * fs
32 * fs
100
IR0
D3
0
MCS[2:0]
128 * fs 192 * fs 256 * fs 384 * fs
64 * fs
011
s
MCS2
).
D2
1
96 * fs
010
MCS1
D1
1
128 * fs 192 * fs
001
2
S sample
MCS0
105/168
000
D0
1