amis-30523 ON Semiconductor, amis-30523 Datasheet - Page 30

• Manufacturer Part Number: amis-30523
• Description: Amis-30523 Product Preview Can Micro-stepping Motor Driver
• Manufacturer: ON Semiconductor

Examples of Combined READ and WRITE Operations
operations are combined. In Figure 28 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
back command in order to verify the data correctly written
as illustrated in Figure 29. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
NOTE:
Figure 29. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by
In the following examples successive READ and WRITE
After the write operation the Master could initiate a read
command or NOT VALID
NOT VALID after POR or RESET
DATA from previous command or
Figure 27. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
command or NOT VALID
after POR or RESET
DATA from previous
The internal data−out shift buffer of the AMIS−30523 is updated with the content of the selected SPI register only at the last (every
eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
after POR or RESET
DATA from previous
CS
DO
CS
DI
Registers are updated with the internal status at the rising
DO
CS
DI
DO
DI
Figure 28. Two Successive READ Commands Followed by a WRITE Command
Registers are Updated with the Internal
Status at the Rising Edge of CS
edge of the internal 523 clock when CS = 1
a READ Back Operation to Verify a Correct WRITE Operation
or NOT VALID
READ DATA
from ADDR4
COMMAND
OLD DATA
or NOT VALID
WRITE DATA
COMMAND
DATA
OLD DATA
to ADDR2
DATA
OLD DATA or NOT VALID
WRITE DATA to ADDR3
COMMAND
DATA
READ DATA
from ADDR5
from ADDR4
COMMAND
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from ADDR2
DATA
DATA
The NEW DATA is written into the corresponding
OLD DATA
NEW DATA
for ADDR2
DATA
DATA
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internal register at the rising edge of CS
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CSB line is high, the first read out byte
might represent old status information.
OLD DATA from ADDR3
NEW DATA for ADDR3
WRITE DATA
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
from ADDR5
COMMAND
to ADDR2
COMMAND
from ADDR2
READ DATA
from ADDR2
DATA
DATA
OLD DATA
DATA
DATA
Registers are Updated with the In-
ternal Status at the Rising Edge of
the Internal 523 Clock when CS = 1
DATA
from ADDR2
NEW DATA
OLD DATA
for ADDR2
COMMAND or
DATA
DATA
from ADDR2
NEW DATA
DUMMY
DATA