amis-30523 ON Semiconductor, amis-30523 Datasheet - Page 27

• Manufacturer Part Number: amis-30523
• Description: Amis-30523 Product Preview Can Micro-stepping Motor Driver
• Manufacturer: ON Semiconductor

CLR Pin (= Hard Reset)
To reset the complete digital inside AMIS−30523, the input
CLR needs to be pulled to logic 1 during minimum time
given by t
This reset function clears all internal registers without the
need of a power−cycle, except in sleep mode. The operation
of all analog circuits is depending on the reset state of the
Table 13. WATCHDOG TIMEOUT INTERVAL AS
FUNCTION OF WDT[3.0]
Index
Logic 0 on CLR pin allows normal operation of the chip.
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
CLR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
. (See Table 6 AC Parameters Motor Driver).
WDT[3:0]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
WDTO
128
160
192
224
256
288
320
352
384
416
448
480
512
32
64
96
(ms)
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digital, charge pump remains active. Logic 0 on CLR pin
resumes normal operation again.
the reset and the PORB/WD pin is not activated. Watchdog
function is reset completely.
Sleep Mode
SPI Control Registers address 03h) is provided to enter a
so−called “sleep mode”. This mode allows reduction of
current−consumption when the motor is not in operation.
The effect of sleep mode is as follows:
•
•
•
•
•
•
current−output capability (I
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, (tcpu) NXT commands can be
issued.
The voltage regulator remains functional during and after
The bit <SLP> in SPI Control Register 2 (See Table 14
The voltage regulator remains active but with reduced
Normal operation is resumed after writing logic ‘0’ to bit
The drivers are put in HiZ
All analog circuits are disabled and in low−power mode
All internal registers are maintaining their logic content
NXT and DIR inputs are forbidden
SPI communication remains possible (slight current
increase during SPI communication)
Oscillator and digital clocks are silent, except during
SPI communication
LOADSLP
). The watchdog timer