amis-30523 ON Semiconductor, amis-30523 Datasheet - Page 28

• Manufacturer Part Number: amis-30523
• Description: Amis-30523 Product Preview Can Micro-stepping Motor Driver
• Manufacturer: ON Semiconductor

microcontroller
AMIS−30523. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30523 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
NOTE:
Transfer Packet:
Address and indicates to AMIS−30523 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30523 in a READ operation.
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
The serial peripheral interface (SPI) allows an external
During a SPI transfer, data is simultaneously transmitted
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
Byte 1 contains the Command and the SPI Register
MSB
Command
At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30523 system clock when CS = High.
Command and SPI Register Address
(Master)
CLK
CS
DO
#CLK Cycle
DI
BYTE 1
SPI Register Address
to
MSB
MSB
communicate
1
Figure 24. Timing Diagram of a SPI Transfer
6
6
2
Figure 25. SPI Transfer Packet
5
5
3
http://onsemi.com
SPI INTERFACE
4
4
with
LSB
4
3
3
28
5
MSB
DO signal is the output from the Slave (AMIS−30523), and
DI signal is the output from the Master. A chip select line
(CSB) allows individual selection of a Slave SPI device in
a multiple−slave system. The CSB line is active low. If
AMIS−30523 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30523 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
communication between master and AMIS−30523:
•
D7
2
The diagram below is both a Master and a Slave timing
2
Two command types can be distinguished in the
READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
6
D6
1
1
7
LSB
LSB
D5
Ì Ì Ì Ì
Ì Ì Ì Ì
Ì Ì Ì
Ì Ì Ì
8
D4
BYTE 2
Data
D3
D2
D1
LSB
D0