stm7007 STMicroelectronics, stm7007 Datasheet - Page 23

• Manufacturer Part Number: stm7007
• Description: Single-chip Hardware Accelerated Encryption Engine For Computer And Peripherals Applications
• Manufacturer: STMicroelectronics

3.3
Power pin VDDPLL2V5:
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Power sequencing
The STM7007 requires proper supply voltage and PGOOD (power good) sequencing for the
internal power-on-self-test and the antifuse blocks.
requirements.
The primary requirement for this device is PGOOD timing; PGOOD must provide a valid
status of the supply voltages during power sequencing.
The PGOOD signal:
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The PGOOD input pin and the PERST# input pin are logically combined internally to ensure
the proper reset state of the device during sequencing.
The 2v5 and 1v2 regulators must be sourced by the 3v3 supply such that the recommended
order of supply sequencing at power up is 1v2 first and then 2v5, and at power down 2v5
drops first, and then 1v2.
Because of an internal ESD protection diode, it is expected that when the 1v2 is applied to
the VDDPLL1V2 pin, the VDDPLL2V5 pin will source voltage at a level equal to the 1v2
voltage minus the forward voltage drop of a diode. To limit the diode current, and to provide
lowpass filtering of the PLL 2V5 power source, place a 30Ω, 5% resistor between the
VDOPLL2V5 pin and the 2V5 source. Position the bypass capacitors close to the
VDDPLL2V5 pin (pad).
Directly connect to the board’s 2.5V common supply dedicated to the PHY
Filter locally using:
–
–
–
remains inactive until all voltages are within their required tolerance bands during
power up
goes inactive before the supply voltages exit their required tolerance bands during
power down
The first indication that power-down sequencing is occurring, is the dropping of the 3v3
input supply voltage.
30Ω resistor (±5% maximum tolerance)
0.1 μF RF capacitor (low series access resistor)
0.01 μF RF capacitor (low series access resistor)
Doc ID 022239 Rev 1
Figure 11
shows the timing and level
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