st802rt1a STMicroelectronics, st802rt1a Datasheet - Page 20

• Manufacturer Part Number: st802rt1a
• Description: 10/100 Real-time Ethernet 3.3 V Transceiver
• Manufacturer: STMicroelectronics

Registers and descriptors description
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be cleared by writing a “0” to bit 10 of the control register, or by resetting the chip. When this
bit is read, it returns a “1” when the chip is in isolate mode; otherwise it returns a “0”.
Restart auto-negotiation: Bit 9 of the control register is a self-clearing bit that allows the
auto-negotiation process to be restarted, regardless of the current status of the auto-
negotiation state machine. In order for this bit to have an effect, auto-negotiation must be
enabled. Writing a “1” to this bit restarts the auto-negotiation, while writing a “0” to this bit
has no effect. Since the bit is self-clearing after only a few cycles, it always returns a “0”
when read.
Full-duplex: By default, the ST802RT1x powers up in half-duplex mode. The chip can be
forced into full-duplex mode by writing a “1” to bit 8 of the control register while auto-
negotiation is disabled. Half-duplex mode can be resumed by writing a “0” to bit 8 of the
control register, or by resetting the chip.
Collision test: The COL pin may be tested during loop-back by activating the collision test
mode. While in this mode, asserting TXEN causes the COL output to go high within 512 bit
times. De-asserting TXEN causes the COL output to go low within 4 bit times. Writing a “1”
to bit 7 of the control register enables the collision test mode. Writing a “0” to this bit or
resetting the chip disables the collision test mode. When this bit is read, it returns a “1” when
the collision test mode has been enabled; otherwise it returns a “0”. This bit should only be
set while in loop-back test mode.
Reserved bits: Write ignored, read as 0.
Doc ID 17049 Rev 1
ST802RT1A, ST802RT1B