st802rt1a STMicroelectronics, st802rt1a Datasheet - Page 15

• Manufacturer Part Number: st802rt1a
• Description: 10/100 Real-time Ethernet 3.3 V Transceiver
• Manufacturer: STMicroelectronics

ST802RT1A, ST802RT1B
Table 4.
Strap pins
The ST802RT1x uses many of the functional pins as strap options. The values of these pins are sampled during
reset hardware or power-up and used to strap the device into specific modes of operation.
The ST802RT1x provides simple strap options to automatically configure some device modes with no device
register configuration necessary. All strap pins have a weak internal pull-up or pull-down. If the default strap value is
needed to be changed, they should not be connected directly to V
be used.
The software reset and the power down through the PD pin cannot be used to change the strap configuration
19, 20,
Pin n°
3, 16,
23
38
28
27
26
46
45
44
43
42
1
8
PHYADDR0
PHYADDR1
PHYADDR2
PHYADDR3
PHYADDR4
MII_CFG0
MII_CFG1
LPBK_EN
AN_EN
Pin functions of the ST802RT1x (continued)
GNDA
Name
AN_0
AN_1
Ground Analog ground
S, PD
S, PD
S, PU
S, PU
S, PD
Type
Loop-back enable
MII Mode Select: This strapping option pair determines the operating mode of
the MAC Data Interface. Default operation (No pull-ups) enables normal MII
mode of operation. Strapping mii_cfg0 high causes the device to be in RMII
mode of operation, determined by the status of the mii_cfg1 strap. Since the
pins include internal pull-downs, the default values are 0.
See
Auto-negotiation enable: When high, this enables auto-negotiation with the
capability set by the an_0 and an_1 pins. When low, this puts the part into
Forced Mode with the capability set by the an_0 and an_1 pins.
an_0 / an_1: These input pins control the forced or advertised operating mode
of the ST802RT1x according to
connecting the input pins to GND (0) or VCC (1) through 2.2 kΩ resistors.
These pins should NEVER be connected directly to GND or V
The value set at this input is latched into the ST802RT1x at Hardware-Reset.
The float/pull-down statuses of these pins are latched into the basic mode
control register and the auto-negotiation advertisement register during
hardware-reset.
The default is 111 since these pins have internal pull-up (see
PHY address [4:0]. These pins are used to provide the address which is latched
into the internal receive mode control register RN14 (0x14h) after the reset.
PHYADDR0 pin has weak internal pull-up resistor.
PHYADDR[4:1] pins have weak internal pull-down resistors.
An external 2.2 kΩ resistor should be used for pull-up/down the pins
Table 6
Doc ID 17049 Rev 1
for details and configurations
CC
Table
or GND and an external 2.2 kΩ resistor should
Description
7. The value on these pins is set by
Table
Pin description
CC
.
7).
15/58