sab-c161ji-lf Infineon Technologies Corporation, sab-c161ji-lf Datasheet - Page 60

• Manufacturer Part Number: sab-c161ji-lf
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

AC Characteristics
Definition of Internal Timing
The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock
Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus
cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C161CS/JC/JI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
56
TCL
f
CPU
C161CS/JC/JI-32R
TCL
. This influence must
TCL
TCL
C161CS/JC/JI-L
TCL
TCL
MCT04338
Figure
V3.0, 2001-01
f
OSC
11).
f
CPU
via
.