sab-c161ji-lf Infineon Technologies Corporation, sab-c161ji-lf Datasheet - Page 22

• Manufacturer Part Number: sab-c161ji-lf
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Note: When one or both of the on-chip CAN Modules or the SDLM are used with the
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161CS/JC/JI’s instructions can be
executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16
bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
Data Sheet
interface lines assigned to Port 4, the interface lines override the segment address
lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e.
address lines A21/A19 … A16. CS lines can be used to increase the total amount
of addressable external memory.
ROM
CPU Block Diagram
32
Data Page Ptr.
Exec. Unit
Instr. Reg.
SYSCON
Instr. Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
STKUN
STKOV
PSW
SP
Pipeline
4-Stage
Barrel - Shifter
Bit-Mask Gen
Code Seg. Ptr.
Mul/Div-HW
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
ALU
MDH
MDL
CPU
18
(16-bit)
Registers
Purpose
General
R15
R0
C161CS/JC/JI-32R
16
16
C161CS/JC/JI-L
V3.0, 2001-01
Internal
RAM
R15
R0
MCB02147