mfrc500 NXP Semiconductors, mfrc500 Datasheet - Page 44

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mfrc500

Manufacturer Part Number
mfrc500
Description
Highly Integrated Iso14443a Reader Ic
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
Highly Integrated ISO 14443A Reader IC
5.2.4.8
controls clock generation for the 90° phase shifted Q-channel clock.
Name: ClockQControl
Description of the bits
Access
Rights
4-0
Bit
7
6
5
ClkQ180Deg
ClockQControl Register
ClkQDelay
ClkQCalib
ClkQ180Deg
Symbol
0
7
r
If the Q-clock is phase shifted more than 180° compared to the I-clock, this bit is
set to 1, otherwise it is 0.
If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and
after data reception from the card.
If this bit is set to 1, no calibration is performed automatically.
This value shall not be changed
This register shows the number of delay elements actually used to generate a 90°
phase shift of the I-clock to obtain the Q-clock.
It can be written directly by the µ-Processor or by the automatic calibration cycle.
ClkQCalib
r/w
6
Address: 0x1F
r/w
5
0
dy
44
4
Product Specification Rev. 3.2;December 2005
Function
dy
3
Reset value: 000XXXXX, 0xXX
ClkQDelay
dy
2
dy
1
MF RC500
PUBLIC
dy
0

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