uja1075a NXP Semiconductors, uja1075a Datasheet - Page 18

• Manufacturer Part Number: uja1075a
• Description: High-speed Can/lin Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1075A
Product data sheet
6.4.3 Watchdog Off behavior
6.5.1 RSTN pin
6.5 System reset
The watchdog is disabled in this state.
The watchdog is in Off mode when:
The following events will cause the SBC to perform a system reset:
A watchdog overflow in Timeout mode requests a CI, if a CI is not already pending.
The UJA1075A provides three signals for dealing with reset events:
A system reset is triggered if the bidirectional RSTN pin is forced LOW for at least t
the microcontroller (external reset). A reset pulse is output on pin RSTN by the SBC when
a system reset is triggered internally.
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the SBC is in Standby mode and bit WMC = 0 or
the SBC is in Off, Overtemp or Sleep modes
the SBC is in Standby mode and bit WMC = 1
the SBC is in any mode and the WDOFF pin is HIGH
V1 undervoltage (reset pulse length selected via external pull-up resistor on RSTN
pin)
An external reset (pin RSTN forced LOW)
Watchdog overflow (Window mode)
Watchdog overflow in Timeout mode with CI pending
Watchdog triggered too early in Window mode
WMC value changed in Normal mode
WDOFF pin state changed
SBC goes to Sleep mode (MC set to 01; see
SBC goes to Sleep mode (MC set to 01; see
STBCC = STBCL = WIC1 = WIC2 = 0
SBC goes to Sleep mode (MC set to 01; see
Software reset (SWR = 1)
SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor
on RSTN pin)
RSTN pin input/output for performing a global ECU system reset or forcing an
external reset
EN pin, a fail-safe global enable output
LIMP pin, a fail-safe limp home output
the SBC is in Normal mode and bit WMC = 1
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 July 2010
High-speed CAN/LIN core system basis chip
Table
Table
Table
5) while pin INTN is driven LOW
5) while
5) while wake-up pending
UJA1075A
© NXP B.V. 2010. All rights reserved.
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