uja1075a NXP Semiconductors, uja1075a Datasheet - Page 17

• Manufacturer Part Number: uja1075a
• Description: High-speed Can/lin Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1075A
Product data sheet
6.4.1 Watchdog Window behavior
6.4.2 Watchdog Timeout behavior
6.4 Watchdog (UJA1075A/xx/WD versions)
Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is
programmed via the NWP control bits in the WD_and_Status register (see
default watchdog period is 128 ms.
A watchdog trigger event is any write access to the WD_and_Status register. When the
watchdog is triggered, the watchdog timer is reset.
In watchdog Window mode, a watchdog trigger event within a closed watchdog window
(i.e. the first half of the window before t
is triggered before the watchdog timer overflows in Timeout or Window mode, or within
the open watchdog window (after t
immediately.
The following watchdog events result in an immediate system reset:
After a watchdog reset (short reset; see
period is selected (NWP = 100). The watchdog can be switched off completely by forcing
pin WDOFF HIGH. The watchdog can also be switched off by setting bit WMC to 1 in
Standby mode. If the watchdog was turned off by setting WMC, any pending interrupt will
re-enable it.
Note that the state of bit WMC cannot be changed in Standby mode if an interrupt is
pending. Any attempt to change WMC when an interrupt is pending will be ignored.
The watchdog runs continuously in Window mode.
If the watchdog overflows, or is triggered in the first half of the watchdog period (less than
t
Watchdog overflow occurs if the watchdog is not triggered within t
the watchdog period.
If the watchdog is triggered in the second half of the watchdog period (at least t
not more than t
The watchdog is in Window mode when pin WDOFF is LOW, the SBC is in Normal mode
and the watchdog mode control bit (WMC) is set to 0.
The watchdog runs continuously in Timeout mode. It can be reset at any time by a
watchdog trigger. If the watchdog overflows, the CI bit is set. If a CI is already pending, a
system reset is performed.
The watchdog is in Timeout mode when pin WDOFF is LOW and:
trig(wd)1
•
•
•
•
•
the watchdog overflows in Window mode
the watchdog is triggered in the first half of the watchdog period in Window mode
the watchdog overflows in Timeout mode while a cyclic interrupt (CI) is pending
the state of the WDOFF pin changes in Normal mode or Standby mode
the watchdog mode control bit (WMC) changes state in Normal mode
after the start of the watchdog period), a system reset will be performed.
trig(wd)2
All information provided in this document is subject to legal disclaimers.
, after the start of the watchdog period), the watchdog will be reset.
Rev. 01 — 9 July 2010
trig(wd)1
trig(wd)1
Section 6.5.1
but before t
High-speed CAN/LIN core system basis chip
) will generate an SBC reset. If the watchdog
trig(wd)2
and
Table
), the timer restarts
11), the default watchdog
trig(wd)2
UJA1075A
© NXP B.V. 2010. All rights reserved.
after the start of
Table
trig(wd)1
4). The
17 of 53
, but