lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 48

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.17.4 Internal RC oscillator (IRC)
7.17.5 PLL0 and PLL2
7.17.6 System PLL1
7.17.7 Reset Generation Unit (RGU)
7.17.8 Power control
7.18 Serial Wire Debug/JTAG
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC4350/30/20/10 use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
PLL0 is a dedicated PLL for the USB0 High-speed controller, and PLL2 can be used as an
audio PLL.
PLL0 and PLL2 are identical PLL blocks. In addition, PLL2 has a fractional rate divider to
control the output frequency with a very fine granularity.
PLL0 and PLL2 accept an input clock frequency from an external oscillator in the range of
14 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
The PLL1 accepts an input clock frequency from an external oscillator in the range of
10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop
to keep the CCO within its frequency range while the PLL is providing the desired output
frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output
clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be
enabled by software. The program must configure and activate the PLL, wait for the PLL
to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs.
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC4350/30/20/10.
The LPC4350/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
The LPC4350/30/20/10 can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
<tbd>
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2010. All rights reserved.
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